JPH034618A - Clock frequency division circuit - Google Patents

Abstract

PURPOSE:To execute optionally even and odd number frequency division by one clock frequency dividing circuit by feeding back an output clock of a 1/2 frequency divider to other input terminal of an exclusive OR gate at odd number frequency division and giving one pulse to an n-counter. CONSTITUTION:When a signal 1 selecting odd number frequency division is inputted to an AND gate 4, an output clock of a 1/2 frequency divider 3 is fed back to other input terminal of the exclusive OR gate 1 through the AND gate 4. Then the exclusive OR gate 1 outputs a pulse with very narrow width depending on a slight time difference between the input clock and the fed-back output clock. Then one pulse is increased in one period of the output clock, resulting in obtaining an odd number of pulses. Thus, an n-counter 2 counts the pulse for each n-pulse to output the clock and the 1/2 frequency divider 3 applies 1/2 frequency division to the clock to attain odd number of frequency division.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a clock frequency dividing circuit that enables even number frequency division and odd number frequency division with a duty of 50%.

[Conventional technology]

Conventionally, a clock frequency divider circuit with a duty of 50% has an n counter 2 that counts n input clocks and an output clock of 2 times the output clock of this n counter 2, as shown in FIG.
It has a configuration in which a 1/2 frequency divider 3 for frequency division is connected in cascade.

As shown in the signal waveforms of each part in FIG. 4, this frequency dividing circuit first counts n input clocks with an n counter 2 and outputs one clock each time. By dividing the frequency by 2, the duty is 50% 2
An n-divided clock can be obtained.

[Problem to be solved by the invention]

The conventional clock frequency divider described above divides the clock output from the n counter 2 by 2 to obtain 2n with a duty of 50%.
Since a frequency-divided clock is obtained, the resulting frequency-divided clock is naturally an even-numbered frequency-divided clock, and an odd-numbered frequency-divided clock cannot be obtained. For this reason, the versatility of the frequency divider is low, and when obtaining a clock equivalent to an odd-number divided clock, it is necessary to increase the frequency of the input clock.
There are problems in that the clock oscillation circuit etc. become complicated and the frequency division operation tends to become unstable.

SUMMARY OF THE INVENTION An object of the present invention is to provide a clock frequency dividing circuit that allows even and odd frequency division to be performed arbitrarily.

[Means to solve the problem]

The clock frequency divider circuit of the present invention includes an exclusive OR gate to which an input clock is input to one input terminal, and an n counter that outputs a clock every time n pulses output from the exclusive OR gate are counted. and a 1/2 frequency divider that divides the output of this n counter by 2, and a 1/2 frequency divider that divides the output of this n counter by 2, and
and a logic gate for inputting the output clock of the frequency divider by two to the other input terminal of the exclusive OR gate.

[Effect]

In this configuration, when the output clock of the 1/2 frequency divider is not fed back to the other input terminal of the exclusive OR gate, it is divided by an even number as before, and when it is fed back, the output clock of the exclusive OR gate is N counter by action! A pulse is added to perform odd frequency division.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of the invention.

In the figure, 1 is an exclusive OR gate, and an input clock (original clock) is input to one input terminal of the gate. 2 is an n counter that counts an arbitrary integer n and generates a pulse of l clock width each time, and the clock (pulse) output from the exclusive OR gate 1 is inputted thereto. 3 is a 1/2 frequency divider, which divides the clock output from the n counter 2 by 2, and divides the clock output from the n counter 2 into a duty ratio of 50.
Outputs % clock. Reference numeral 4 designates an AND gate, into which the output clock of the 1/2 frequency divider 3 is inputted to one input terminal, and an odd/even number selection signal is inputted to the other input terminal. The output of the AND gate 4 is configured to be input to the other input terminal of the exclusive OR gate 1.

The operation of the frequency divider circuit having this configuration will be explained using the signal waveform diagram of FIG. 2.

Assume that the n counter 2 is now set to a count value of 4. Then, the n counter 2 counts the clocks input through the exclusive OR gate 1, and outputs a pulse with a width of one clock every n counts. And l/
The 2 frequency divider 3 inverts each pulse and divides the frequency by 2.
□As a result, a clock of 450% DEATE is output.

Here, a signal ('
1''), the output clock of the 1/2 frequency divider 3 is fed back to the other input terminal of the exclusive OR gate l through the AND gate 4. 1
When the input clock and the fed back output clock are slightly different from each other, they are scratched by opening the lid and output a short pulse.

Since these short pulses occur at the rising and falling edges of the output clock,
The number of pulses increases by one within the period, resulting in an odd number of pulses. Therefore, since the n counter 2 counts this pulse every n and outputs a clock, and the 1/2 frequency divider 3 divides the frequency by 2, the frequency is divided by an odd number, in this example, by 7. A round will be held.

It goes without saying that by changing the count setting value of the n counter 2, it is possible to divide the frequency by an arbitrary odd number.

〔Effect of the invention〕

As explained above, in the present invention, when frequency is divided by an odd number, one pulse is added to the n counter in order to feed back the output clock of the 1/2 frequency divider to the other input terminal of the exclusive OR gate. Thus, odd number division is realized. This results in 1
Even-number and odd-number frequency division can be performed arbitrarily using a single clock frequency dividing circuit, and versatility can be increased. Furthermore, a high-frequency clock is not required, and highly stable odd-number frequency division operation can be obtained.

[Brief Description of the Drawings] Figure 1 is a block diagram of an embodiment of the present invention, Figure 2 is a signal waveform diagram of each part of Figure 1, and Figure 3 is a block diagram of a conventional clock frequency divider circuit. , FIG. 4 is a signal waveform diagram of each part in FIG. 3.

Claims (1)

[Claims] 1. An exclusive OR gate to which an input clock is input to one input terminal, an n counter that outputs a clock every n counts of pulses output from this exclusive OR gate, and the output of this n counter and a logic gate that inputs the output clock of the 1/2 frequency divider to the other input terminal of the exclusive OR gate when the frequency is divided by an odd number. Clock divider circuit.