JPS57195400A - Storage device - Google Patents

Storage device

Info

Publication number
JPS57195400A
JPS57195400A JP56081584A JP8158481A JPS57195400A JP S57195400 A JPS57195400 A JP S57195400A JP 56081584 A JP56081584 A JP 56081584A JP 8158481 A JP8158481 A JP 8158481A JP S57195400 A JPS57195400 A JP S57195400A
Authority
JP
Japan
Prior art keywords
data
control circuit
error detection
detection signal
storage device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP56081584A
Other languages
Japanese (ja)
Inventor
Kenji Ishikawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP56081584A priority Critical patent/JPS57195400A/en
Publication of JPS57195400A publication Critical patent/JPS57195400A/en
Pending legal-status Critical Current

Links

Landscapes

  • Detection And Correction Of Errors (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)

Abstract

PURPOSE: To simplify the constitution of the data order control circuit of an external device for controlling data outputted from storage devices, by applying an error detection signal even to the storage device of the opposite system if the storage device of one system.
CONSTITUTION: An error detection signal 1'-2 from a 1'-system MMU1 is transferred to a 0'-system MMU0' and the data control circuit 8 of a buffer controller 4'. Since the error detection signal 1'-2 is inputted as a signal 31 to the main memory (MMU) of the system 0', the read data is switched from the transfer of input data 22 over to the correction data transfer 27 by a switching signal 32, outputted from an error control circuit 30, as well as the storage device of the system 1'. Therefore, the data control circuit 8 only controls a switching signal 8-1 by delaying respective read requests from 0'-system and 1'-system CPUs to 0' system and 1'-system MMUs by the same time in the order of the requests according to the error detection signal 1'-2.
COPYRIGHT: (C)1982,JPO&Japio
JP56081584A 1981-05-27 1981-05-27 Storage device Pending JPS57195400A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56081584A JPS57195400A (en) 1981-05-27 1981-05-27 Storage device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56081584A JPS57195400A (en) 1981-05-27 1981-05-27 Storage device

Publications (1)

Publication Number Publication Date
JPS57195400A true JPS57195400A (en) 1982-12-01

Family

ID=13750366

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56081584A Pending JPS57195400A (en) 1981-05-27 1981-05-27 Storage device

Country Status (1)

Country Link
JP (1) JPS57195400A (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5654696A (en) * 1979-10-05 1981-05-14 Nec Corp Memory device

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5654696A (en) * 1979-10-05 1981-05-14 Nec Corp Memory device

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