JPS5597623A - Control method for input/output device - Google Patents

Control method for input/output device

Info

Publication number
JPS5597623A
JPS5597623A JP433079A JP433079A JPS5597623A JP S5597623 A JPS5597623 A JP S5597623A JP 433079 A JP433079 A JP 433079A JP 433079 A JP433079 A JP 433079A JP S5597623 A JPS5597623 A JP S5597623A
Authority
JP
Japan
Prior art keywords
information
address
error
chc
cpu
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP433079A
Other languages
Japanese (ja)
Other versions
JPS6013498B2 (en
Inventor
Norio Arai
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP54004330A priority Critical patent/JPS6013498B2/en
Publication of JPS5597623A publication Critical patent/JPS5597623A/en
Publication of JPS6013498B2 publication Critical patent/JPS6013498B2/en
Expired legal-status Critical Current

Links

Abstract

PURPOSE: To reduce the load of the CPU and the time required for retransfer by securing the retransfer of the information with no intervention of the CPU in case the error or the fault is detected at the IOC or IO.
CONSTITUTION: Floppy disk FD is provided along with memory circuits 32 and 33 which are newly added in this invention. In case some error is detected at the FDC when the information is read out of FD via the IO order at the CPU to be written into main memory MM via the CHC, the FDC requests the transfer of the address into which the error information is to be written to the CHC. Then the address transferred is stored in memory circuit 32, and the head address of the information block to which the error information belongs is calculated based on the address stored in the memory circuit. This head address is then transferred to the CHC, and then the information given from the head of the block is transferred again.
COPYRIGHT: (C)1980,JPO&Japio
JP54004330A 1979-01-18 1979-01-18 How to control input/output devices Expired JPS6013498B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP54004330A JPS6013498B2 (en) 1979-01-18 1979-01-18 How to control input/output devices

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP54004330A JPS6013498B2 (en) 1979-01-18 1979-01-18 How to control input/output devices

Publications (2)

Publication Number Publication Date
JPS5597623A true JPS5597623A (en) 1980-07-25
JPS6013498B2 JPS6013498B2 (en) 1985-04-08

Family

ID=11581426

Family Applications (1)

Application Number Title Priority Date Filing Date
JP54004330A Expired JPS6013498B2 (en) 1979-01-18 1979-01-18 How to control input/output devices

Country Status (1)

Country Link
JP (1) JPS6013498B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5727326A (en) * 1980-07-28 1982-02-13 Fujitsu Ltd Control device for data transfer

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5727326A (en) * 1980-07-28 1982-02-13 Fujitsu Ltd Control device for data transfer
JPS6243224B2 (en) * 1980-07-28 1987-09-11 Fujitsu Ltd

Also Published As

Publication number Publication date
JPS6013498B2 (en) 1985-04-08

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