JPS57194628A - Initializing circuit - Google Patents

Initializing circuit

Info

Publication number
JPS57194628A
JPS57194628A JP8040781A JP8040781A JPS57194628A JP S57194628 A JPS57194628 A JP S57194628A JP 8040781 A JP8040781 A JP 8040781A JP 8040781 A JP8040781 A JP 8040781A JP S57194628 A JPS57194628 A JP S57194628A
Authority
JP
Japan
Prior art keywords
circuit
circuits
difference
delay
time
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP8040781A
Other languages
Japanese (ja)
Inventor
Akira Yazawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP8040781A priority Critical patent/JPS57194628A/en
Publication of JPS57194628A publication Critical patent/JPS57194628A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/22—Modifications for ensuring a predetermined initial state when the supply voltage has been applied

Landscapes

  • Electronic Switches (AREA)

Abstract

PURPOSE:To secure resetting operation by connecting two circuits in parallel, and generating a pulse which has time width equivalent to the difference in propagation time between said circuits. CONSTITUTION:A delay circuit 11 and a delay circuit 12 are each constituted by connecting plural inverting circuit in series. The circuits 1 and 12 differ in the number of inverting circuit to have a difference in delay time. The outputs of the circuits 11 and 12 are inputted to a logical circuit. As the logical circuit 13, an AND circuit, an NAND circuit, an OR circuit, an NOR circuit, etc., are usable. When an input signal is applied to an input terminal 15, a pulse signal which has time width equivalent to the difference in delay time between the circuits 11 and 12 appears at an output terminal 16.
JP8040781A 1981-05-27 1981-05-27 Initializing circuit Pending JPS57194628A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8040781A JPS57194628A (en) 1981-05-27 1981-05-27 Initializing circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8040781A JPS57194628A (en) 1981-05-27 1981-05-27 Initializing circuit

Publications (1)

Publication Number Publication Date
JPS57194628A true JPS57194628A (en) 1982-11-30

Family

ID=13717433

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8040781A Pending JPS57194628A (en) 1981-05-27 1981-05-27 Initializing circuit

Country Status (1)

Country Link
JP (1) JPS57194628A (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5416963A (en) * 1977-07-07 1979-02-07 Mitsubishi Electric Corp Differetiating circuit
JPS54158843A (en) * 1978-06-06 1979-12-15 Nippon Telegr & Teleph Corp <Ntt> Power-on reset circuit

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5416963A (en) * 1977-07-07 1979-02-07 Mitsubishi Electric Corp Differetiating circuit
JPS54158843A (en) * 1978-06-06 1979-12-15 Nippon Telegr & Teleph Corp <Ntt> Power-on reset circuit

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