JPS57143919A - Waveform shaping circuit - Google Patents

Waveform shaping circuit

Info

Publication number
JPS57143919A
JPS57143919A JP56029328A JP2932881A JPS57143919A JP S57143919 A JPS57143919 A JP S57143919A JP 56029328 A JP56029328 A JP 56029328A JP 2932881 A JP2932881 A JP 2932881A JP S57143919 A JPS57143919 A JP S57143919A
Authority
JP
Japan
Prior art keywords
circuit
group
constitute
input
cascaded
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP56029328A
Other languages
Japanese (ja)
Inventor
Hitoshi Imagawa
Kuniyasu Kawarada
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Telegraph and Telephone Corp
Original Assignee
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Telegraph and Telephone Corp filed Critical Nippon Telegraph and Telephone Corp
Priority to JP56029328A priority Critical patent/JPS57143919A/en
Publication of JPS57143919A publication Critical patent/JPS57143919A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/125—Discriminating pulses
    • H03K5/1252—Suppression or limitation of noise or interference

Landscapes

  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Manipulation Of Pulses (AREA)

Abstract

PURPOSE:To facilitate IC-implementation and to achieve economization by shaping the waveform of an input pulse without using any capacitor and resistance, by constituting a simple logical circuit. CONSTITUTION:Cascaded FFs 23-25 in the 1st FF group constitute the 1st circuit. A three-input NAND gate 29 which inputs output signals from two-input NAND gates 26-28 constitutes the 2nd circuit which discriminates coincidence of the output results of >=M sets (N>M) among N sets of outputs of the 1st FF group. Then, the 1st and 2nd circuits constitute a circuit part X which absorbs an impulsive noise. Cascaded FFs 30 and 31 constitute the 3rd circuit consisting of the 2nd FF group cascaded in K sets. A three-input OR gate 32 constitutes the 4th circuit which ORs output results from the 2nd FF group and the output results of the 2nd circuit. Then, the 3rd and 4th circuits constitute a circuit part Y which shapes the pulse time width of an input signal from the circuit part X.
JP56029328A 1981-03-03 1981-03-03 Waveform shaping circuit Pending JPS57143919A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56029328A JPS57143919A (en) 1981-03-03 1981-03-03 Waveform shaping circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56029328A JPS57143919A (en) 1981-03-03 1981-03-03 Waveform shaping circuit

Publications (1)

Publication Number Publication Date
JPS57143919A true JPS57143919A (en) 1982-09-06

Family

ID=12273160

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56029328A Pending JPS57143919A (en) 1981-03-03 1981-03-03 Waveform shaping circuit

Country Status (1)

Country Link
JP (1) JPS57143919A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0472808A (en) * 1990-07-12 1992-03-06 Nec Corp Noise elimination circuit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0472808A (en) * 1990-07-12 1992-03-06 Nec Corp Noise elimination circuit

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