JPS5685930A - Pulse width discriminating circuit - Google Patents

Pulse width discriminating circuit

Info

Publication number
JPS5685930A
JPS5685930A JP15501079A JP15501079A JPS5685930A JP S5685930 A JPS5685930 A JP S5685930A JP 15501079 A JP15501079 A JP 15501079A JP 15501079 A JP15501079 A JP 15501079A JP S5685930 A JPS5685930 A JP S5685930A
Authority
JP
Grant status
Application
Patent type
Prior art keywords
circuit
circuits
pulse width
output
delay time
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP15501079A
Inventor
Norio Murakami
Kazuo Murano
Toshitaka Tsuda
Kazuo Yamaguchi
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date

Links

Classifications

    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R29/00Arrangements for measuring or indicating electric quantities not covered by groups G01R19/00 - G01R27/00
    • G01R29/02Measuring characteristics of individual pulses, e.g. deviation from pulse flatness, rise time, duration
    • G01R29/027Indicating that a pulse characteristic is either above or below a predetermined value or within or beyond a predetermined range of values
    • G01R29/0273Indicating that a pulse characteristic is either above or below a predetermined value or within or beyond a predetermined range of values the pulse characteristic being duration, i.e. width (indicating that frequency of pulses is above or below a certain limit)

Abstract

PURPOSE:To make it possible to easily integrate the circuit, by setting and resetting the FF by the respective even-and odd-ordered AND output signals of optional numbers of plural inverting circuits which have been cascaded. CONSTITUTION:The even output signals c, e, g, i, k of optional number of the inverting circuits N1-N16 whose delay time is equal are input to the NAND circuit 1, and the odd-ordered output signals b, d, f, h, j of optional numbers are input to the NAND circuit 2. The respective signals m, l of the circuits 1, 2 are made set and reset signals of the FF which is composed of the NAND circuits 3, 4, and the circuits 1-4 have an equal delay time. According to this constitution, a signal having pulse width which is larger than the delay time by the circuits N1-N16 is output as an output signal (n), as it is from the circuit 3 after said delay time, a signal having smaller pulse width than said signal is not output, and therefore, the pulse width can be discriminated. Since this circuit is constituted of a gate circuit, it is possible to integrate it.
JP15501079A 1979-11-30 1979-11-30 Pulse width discriminating circuit Pending JPS5685930A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15501079A JPS5685930A (en) 1979-11-30 1979-11-30 Pulse width discriminating circuit

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
JP15501079A JPS5685930A (en) 1979-11-30 1979-11-30 Pulse width discriminating circuit
CA 365338 CA1159129A (en) 1979-11-27 1980-11-24 Asynchronous transmission system for binary-coded information
US06210850 US4347617A (en) 1979-11-27 1980-11-26 Asynchronous transmission system for binary-coded information
GB8037943A GB2064922B (en) 1979-11-27 1980-11-26 Asynchronous transmission system for binary-coded information

Publications (1)

Publication Number Publication Date
JPS5685930A true true JPS5685930A (en) 1981-07-13

Family

ID=15596706

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15501079A Pending JPS5685930A (en) 1979-11-30 1979-11-30 Pulse width discriminating circuit

Country Status (1)

Country Link
JP (1) JPS5685930A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6299991A (en) * 1985-10-25 1987-05-09 Hitachi Ltd Semiconductor storage device
US5589784A (en) * 1992-03-31 1996-12-31 Texas Instruments Incorporated Method and apparatus for detecting changes in a clock signal to static states
JP2010076127A (en) * 2008-09-24 2010-04-08 Kawasaki Microelectronics Inc Synchronizing signal detecting circuit and semiconductor integrated circuit

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5136095A (en) * 1974-09-20 1976-03-26 Matsushita Electric Ind Co Ltd Hyojisochi

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5136095A (en) * 1974-09-20 1976-03-26 Matsushita Electric Ind Co Ltd Hyojisochi

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6299991A (en) * 1985-10-25 1987-05-09 Hitachi Ltd Semiconductor storage device
US5589784A (en) * 1992-03-31 1996-12-31 Texas Instruments Incorporated Method and apparatus for detecting changes in a clock signal to static states
JP2010076127A (en) * 2008-09-24 2010-04-08 Kawasaki Microelectronics Inc Synchronizing signal detecting circuit and semiconductor integrated circuit

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