JPS57186329A - Exposing method - Google Patents

Exposing method

Info

Publication number
JPS57186329A
JPS57186329A JP56071017A JP7101781A JPS57186329A JP S57186329 A JPS57186329 A JP S57186329A JP 56071017 A JP56071017 A JP 56071017A JP 7101781 A JP7101781 A JP 7101781A JP S57186329 A JPS57186329 A JP S57186329A
Authority
JP
Japan
Prior art keywords
film
region
under
substrate
exposure
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP56071017A
Other languages
Japanese (ja)
Inventor
Hatsuo Nakamura
Chiharu Kato
Toshihiro Abe
Shigeo Furuguchi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP56071017A priority Critical patent/JPS57186329A/en
Publication of JPS57186329A publication Critical patent/JPS57186329A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Projection-Type Copiers In General (AREA)
  • Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)

Abstract

PURPOSE:To obtain a resist film pattern having no defect such as a pinhole or the like by moving a substrate at the prescribed distance in the prescribed direction after the exposure and again exposing it when forming a resin film on a semiconductor substrate to be etched, covering the film with a photomask of the predetermined pattern and exposing the resist film. CONSTITUTION:An insulating film 1 to be patterned is covered on a semiconductor substrate, and when an ultraviolet light is emitted onto the substrate, the emitted region is cured, and the unemitted region is coated with a negative type resist film 2 to be removable by developing. Subsequently, a photomask 3 having a light transmission region 3a and an opaque region 3b is placed on the film, an ultraviolet light 4 is exposed from above, the film 2 directly under the region 3a is crosslinked and cured, and the film 2 under the region 3b is set in the state capable of being developed. If an exposure disturbing substance 5 such as dusts or the like is adhered onto the region 3a at this time, the film 2 under the substance becomes the same state as the film 2 under the region 3b. Accordingly, the substrate 1 is moved after the first exposure, and is again exposed at the region under the substance 5.
JP56071017A 1981-05-12 1981-05-12 Exposing method Pending JPS57186329A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56071017A JPS57186329A (en) 1981-05-12 1981-05-12 Exposing method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56071017A JPS57186329A (en) 1981-05-12 1981-05-12 Exposing method

Publications (1)

Publication Number Publication Date
JPS57186329A true JPS57186329A (en) 1982-11-16

Family

ID=13448319

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56071017A Pending JPS57186329A (en) 1981-05-12 1981-05-12 Exposing method

Country Status (1)

Country Link
JP (1) JPS57186329A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2006025266A1 (en) * 2004-08-30 2006-03-09 Toray Industries, Inc. Display member exposing method and plasma display member manufacturing method

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2006025266A1 (en) * 2004-08-30 2006-03-09 Toray Industries, Inc. Display member exposing method and plasma display member manufacturing method
US8263319B2 (en) 2004-08-30 2012-09-11 Panasonic Corporation Display member exposing method and plasma display member manufacturing method

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