JPS57177539A - Forming method for multiple layer wiring - Google Patents
Forming method for multiple layer wiringInfo
- Publication number
- JPS57177539A JPS57177539A JP6199981A JP6199981A JPS57177539A JP S57177539 A JPS57177539 A JP S57177539A JP 6199981 A JP6199981 A JP 6199981A JP 6199981 A JP6199981 A JP 6199981A JP S57177539 A JPS57177539 A JP S57177539A
- Authority
- JP
- Japan
- Prior art keywords
- aperture
- wiring
- film
- multiple layer
- plating
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Abstract
PURPOSE:To obtain a highly reliable multiple layer wiring by a method wherein an aperture is provided in an interlayer insulator film, at the least the aperture wall is covered with a thin metal film same as or different from the metal constituting the lower wiring, the aperture is filled up by means of nonelectrolytic plating for a flush surface, and then an upper wiring layer is provided. CONSTITUTION:An SiO2 layer 22, an Al wiring 23, a CVDS SiO2 layer 24 are successively laid on a wafer 21, after device formation. Then a resist mask 25 is formed and an aperture 30' is provided thanks to a CF4+O2 mixture applied through an aperture 30. Formation follows of a 200-500Angstrom thick Al film 26 by vapor plating. Next, the resist 25 is removed with the Al film 26 left on the wall of the aperture 30'. Non-electrolytic Ni plating is done to fill up the aperture 30' with Ni for a flush wafer surface. Lastly, an upper Al wiring 28 is provided. Repetition of this process results in a highly reliable multiple layer wiring with the wafer surface flat.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP6199981A JPS57177539A (en) | 1981-04-24 | 1981-04-24 | Forming method for multiple layer wiring |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP6199981A JPS57177539A (en) | 1981-04-24 | 1981-04-24 | Forming method for multiple layer wiring |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS57177539A true JPS57177539A (en) | 1982-11-01 |
Family
ID=13187414
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP6199981A Pending JPS57177539A (en) | 1981-04-24 | 1981-04-24 | Forming method for multiple layer wiring |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS57177539A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH02341A (en) * | 1987-02-02 | 1990-01-05 | Seiko Epson Corp | Semiconductor device |
JPH0645210A (en) * | 1992-07-27 | 1994-02-18 | Nec Corp | Method of forming multi-layer wiring |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS4923583A (en) * | 1972-06-23 | 1974-03-02 |
-
1981
- 1981-04-24 JP JP6199981A patent/JPS57177539A/en active Pending
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS4923583A (en) * | 1972-06-23 | 1974-03-02 |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH02341A (en) * | 1987-02-02 | 1990-01-05 | Seiko Epson Corp | Semiconductor device |
JPH0645210A (en) * | 1992-07-27 | 1994-02-18 | Nec Corp | Method of forming multi-layer wiring |
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