JPS57166739A - Logical circuit - Google Patents

Logical circuit

Info

Publication number
JPS57166739A
JPS57166739A JP56052225A JP5222581A JPS57166739A JP S57166739 A JPS57166739 A JP S57166739A JP 56052225 A JP56052225 A JP 56052225A JP 5222581 A JP5222581 A JP 5222581A JP S57166739 A JPS57166739 A JP S57166739A
Authority
JP
Japan
Prior art keywords
turned
inv1
input signal
signal
clock signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP56052225A
Other languages
Japanese (ja)
Inventor
Seiji Igarashi
Giichi Kato
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP56052225A priority Critical patent/JPS57166739A/en
Publication of JPS57166739A publication Critical patent/JPS57166739A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
    • H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
    • H03K19/096—Synchronous circuits, i.e. using clock signals

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Logic Circuits (AREA)

Abstract

PURPOSE:To prevent an input signal holding type circuit from error operation due to noises by connecting a capacitance element to a returning line. CONSTITUTION:When a clock signal phi1 is turned to ''H'' and a clock signal phi2 is turned to ''L'', an input signal passes through a transistor Q5 and inputted to an inverter INV1. If the input signal is ''L'', the output of the INV1 is turned to ''H'' and inverted by an inverter INV2. When the clock signal phi1 is turned to ''L'' and the clock signal phi2 is turned to ''H'', the output signal ''L'' of the INV2 passes through a transistor Q6 and is applied to the input of the INV1, holding the input signal. Even if a noise pulse of about 100ns is generated in an electric power line, the output signal of the INV1 is held by the load capacitance C of the INV1, so that the input signal of the INV2 is not changed.
JP56052225A 1981-04-07 1981-04-07 Logical circuit Pending JPS57166739A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56052225A JPS57166739A (en) 1981-04-07 1981-04-07 Logical circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56052225A JPS57166739A (en) 1981-04-07 1981-04-07 Logical circuit

Publications (1)

Publication Number Publication Date
JPS57166739A true JPS57166739A (en) 1982-10-14

Family

ID=12908794

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56052225A Pending JPS57166739A (en) 1981-04-07 1981-04-07 Logical circuit

Country Status (1)

Country Link
JP (1) JPS57166739A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4594519A (en) * 1982-10-25 1986-06-10 Tokyo Shibaura Denki Kabushiki Kaisha Low power consumption, high speed CMOS signal input circuit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4594519A (en) * 1982-10-25 1986-06-10 Tokyo Shibaura Denki Kabushiki Kaisha Low power consumption, high speed CMOS signal input circuit

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