JPS57166726A - Output circuit for boosted signal - Google Patents

Output circuit for boosted signal

Info

Publication number
JPS57166726A
JPS57166726A JP56051413A JP5141381A JPS57166726A JP S57166726 A JPS57166726 A JP S57166726A JP 56051413 A JP56051413 A JP 56051413A JP 5141381 A JP5141381 A JP 5141381A JP S57166726 A JPS57166726 A JP S57166726A
Authority
JP
Japan
Prior art keywords
vcc
phi
charge
signal
time
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP56051413A
Other languages
English (en)
Japanese (ja)
Other versions
JPH038125B2 (enExample
Inventor
Mamoru Nakahira
Hideyo Kanayama
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP56051413A priority Critical patent/JPS57166726A/ja
Publication of JPS57166726A publication Critical patent/JPS57166726A/ja
Publication of JPH038125B2 publication Critical patent/JPH038125B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0008—Arrangements for reducing power consumption
    • H03K19/0016—Arrangements for reducing power consumption by using a control or a clock signal, e.g. in order to apply power supply

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Manipulation Of Pulses (AREA)
  • Electronic Switches (AREA)
  • Logic Circuits (AREA)
JP56051413A 1981-04-06 1981-04-06 Output circuit for boosted signal Granted JPS57166726A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56051413A JPS57166726A (en) 1981-04-06 1981-04-06 Output circuit for boosted signal

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56051413A JPS57166726A (en) 1981-04-06 1981-04-06 Output circuit for boosted signal

Publications (2)

Publication Number Publication Date
JPS57166726A true JPS57166726A (en) 1982-10-14
JPH038125B2 JPH038125B2 (enExample) 1991-02-05

Family

ID=12886235

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56051413A Granted JPS57166726A (en) 1981-04-06 1981-04-06 Output circuit for boosted signal

Country Status (1)

Country Link
JP (1) JPS57166726A (enExample)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6132125A (ja) * 1984-07-25 1986-02-14 Hitachi Ltd 電流制御回路
EP0647944A3 (en) * 1993-10-06 1995-08-23 Nec Corp Output circuit for memory circuit with multiple output bits.

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS55136723A (en) * 1979-04-11 1980-10-24 Mitsubishi Electric Corp Booster circuit

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS55136723A (en) * 1979-04-11 1980-10-24 Mitsubishi Electric Corp Booster circuit

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6132125A (ja) * 1984-07-25 1986-02-14 Hitachi Ltd 電流制御回路
EP0647944A3 (en) * 1993-10-06 1995-08-23 Nec Corp Output circuit for memory circuit with multiple output bits.

Also Published As

Publication number Publication date
JPH038125B2 (enExample) 1991-02-05

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