JPS57164342A - Interruption processing retrial control system - Google Patents

Interruption processing retrial control system

Info

Publication number
JPS57164342A
JPS57164342A JP56048559A JP4855981A JPS57164342A JP S57164342 A JPS57164342 A JP S57164342A JP 56048559 A JP56048559 A JP 56048559A JP 4855981 A JP4855981 A JP 4855981A JP S57164342 A JPS57164342 A JP S57164342A
Authority
JP
Japan
Prior art keywords
interruption
retrial
processing
interruption processing
flag
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP56048559A
Other languages
Japanese (ja)
Other versions
JPS6132701B2 (en
Inventor
Takio Tezuka
Katsumi Onishi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP56048559A priority Critical patent/JPS57164342A/en
Publication of JPS57164342A publication Critical patent/JPS57164342A/en
Publication of JPS6132701B2 publication Critical patent/JPS6132701B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/14—Error detection or correction of the data by redundancy in operation

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Retry When Errors Occur (AREA)

Abstract

PURPOSE:To relieve the case wherein an error is simply a tentative trouble only, by providing two interruption retrial flags indicating the state of interruption processing retrial during interruption processing. CONSTITUTION:An interruption retrial flag (I)F1 is set to allow the interruption retrial during the interruption processing. If an error ER takes place, since an interruption processing retrial control section RTYCTL permits error detection with a signal line 37, the instruction of interruption retrial processing is given to an interruption processing control section RCTL. The RCTL makes a present program status word PSW restart address calculation and gives the rewrite instruction to an old program status word OPSW to a processing section PCTL to set an interruption retrial flag (II)F2 with the completion of rewrite. That is, this flag F2 inhibits the write to a main storage device by a memory access control section MAC. Thus, after the setting of the OPSW, the address of restart instruction can not be destroyed regardless of how many times the interruption processing retrials take place.
JP56048559A 1981-03-31 1981-03-31 Interruption processing retrial control system Granted JPS57164342A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56048559A JPS57164342A (en) 1981-03-31 1981-03-31 Interruption processing retrial control system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56048559A JPS57164342A (en) 1981-03-31 1981-03-31 Interruption processing retrial control system

Publications (2)

Publication Number Publication Date
JPS57164342A true JPS57164342A (en) 1982-10-08
JPS6132701B2 JPS6132701B2 (en) 1986-07-29

Family

ID=12806733

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56048559A Granted JPS57164342A (en) 1981-03-31 1981-03-31 Interruption processing retrial control system

Country Status (1)

Country Link
JP (1) JPS57164342A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2020086897A (en) * 2018-11-26 2020-06-04 富士通株式会社 Arithmetic processing device and method for controlling arithmetic processing device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2020086897A (en) * 2018-11-26 2020-06-04 富士通株式会社 Arithmetic processing device and method for controlling arithmetic processing device
US11372712B2 (en) 2018-11-26 2022-06-28 Fujitsu Limited Processing device and method of controlling processing device

Also Published As

Publication number Publication date
JPS6132701B2 (en) 1986-07-29

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