JPS57117195A - Computer device - Google Patents

Computer device

Info

Publication number
JPS57117195A
JPS57117195A JP56002505A JP250581A JPS57117195A JP S57117195 A JPS57117195 A JP S57117195A JP 56002505 A JP56002505 A JP 56002505A JP 250581 A JP250581 A JP 250581A JP S57117195 A JPS57117195 A JP S57117195A
Authority
JP
Japan
Prior art keywords
memory device
abnormity
memory
address
outputted
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP56002505A
Other languages
Japanese (ja)
Inventor
Yuji Ebihara
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP56002505A priority Critical patent/JPS57117195A/en
Publication of JPS57117195A publication Critical patent/JPS57117195A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G11C29/74—Masking faults in memories by using spares or by reconfiguring using duplex memories, i.e. using dual copies

Landscapes

  • Techniques For Improving Reliability Of Storages (AREA)
  • Hardware Redundancy (AREA)

Abstract

PURPOSE:To enable immediate backup if a memory device is in failure, by arbitrarily designating the address of a spare memory device and enabling abnormity check of memory in usage state. CONSTITUTION:If a failure or abnormity is present in a specific address of a spare memory device 12, it is controlled with a discrimination circuit of a memory control 11. The error message is outputted and the memory address having an abnormity and the content of data are outputted. The data of a main memory device 6 is transferred to a CPU5 as it is, and a computer can continue the operation without being stopped. Similarly, the abnormity of memory device is continuously checked during computer processing. Thus, if an abnormity takes place in the memory device, backup is immediately made.
JP56002505A 1981-01-10 1981-01-10 Computer device Pending JPS57117195A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56002505A JPS57117195A (en) 1981-01-10 1981-01-10 Computer device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56002505A JPS57117195A (en) 1981-01-10 1981-01-10 Computer device

Publications (1)

Publication Number Publication Date
JPS57117195A true JPS57117195A (en) 1982-07-21

Family

ID=11531212

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56002505A Pending JPS57117195A (en) 1981-01-10 1981-01-10 Computer device

Country Status (1)

Country Link
JP (1) JPS57117195A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5948899A (en) * 1982-09-09 1984-03-21 Ishida Scales Mfg Co Ltd Error checking method of ram
JPS6210746A (en) * 1985-07-08 1987-01-19 Hitachi Cable Ltd Non-volatile ram checking method

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5948899A (en) * 1982-09-09 1984-03-21 Ishida Scales Mfg Co Ltd Error checking method of ram
JPS6210746A (en) * 1985-07-08 1987-01-19 Hitachi Cable Ltd Non-volatile ram checking method

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