JPS57150227A - Buffer circuit - Google Patents

Buffer circuit

Info

Publication number
JPS57150227A
JPS57150227A JP56035724A JP3572481A JPS57150227A JP S57150227 A JPS57150227 A JP S57150227A JP 56035724 A JP56035724 A JP 56035724A JP 3572481 A JP3572481 A JP 3572481A JP S57150227 A JPS57150227 A JP S57150227A
Authority
JP
Japan
Prior art keywords
driving
turned
level
cont
high impedance
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP56035724A
Other languages
English (en)
Japanese (ja)
Other versions
JPH0456491B2 (enrdf_load_html_response
Inventor
Mineo Akashi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP56035724A priority Critical patent/JPS57150227A/ja
Publication of JPS57150227A publication Critical patent/JPS57150227A/ja
Publication of JPH0456491B2 publication Critical patent/JPH0456491B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
    • H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
    • H03K19/09425—Multistate logic
    • H03K19/09429—Multistate logic one of the states being the high impedance or floating state

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Dram (AREA)
  • Logic Circuits (AREA)
  • Small-Scale Networks (AREA)
JP56035724A 1981-03-12 1981-03-12 Buffer circuit Granted JPS57150227A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56035724A JPS57150227A (en) 1981-03-12 1981-03-12 Buffer circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56035724A JPS57150227A (en) 1981-03-12 1981-03-12 Buffer circuit

Related Child Applications (1)

Application Number Title Priority Date Filing Date
JP3266725A Division JPH0812996B2 (ja) 1991-07-15 1991-07-15 バッファ回路

Publications (2)

Publication Number Publication Date
JPS57150227A true JPS57150227A (en) 1982-09-17
JPH0456491B2 JPH0456491B2 (enrdf_load_html_response) 1992-09-08

Family

ID=12449795

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56035724A Granted JPS57150227A (en) 1981-03-12 1981-03-12 Buffer circuit

Country Status (1)

Country Link
JP (1) JPS57150227A (enrdf_load_html_response)

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58172022A (ja) * 1982-03-29 1983-10-08 インタ−ナシヨナル　ビジネス　マシ−ンズ　コ−ポレ−シヨン 駆動回路
JPS59229923A (ja) * 1983-06-13 1984-12-24 Hitachi Ltd 集積回路用論理回路
JPS59229924A (ja) * 1983-06-13 1984-12-24 Hitachi Ltd 集積回路用論理回路
JPS61212116A (ja) * 1985-03-15 1986-09-20 Nec Corp 半導体集積回路
JPH03142788A (ja) * 1989-10-27 1991-06-18 Nec Corp 半導体メモリ用センスアンプ回路
JPH0547185A (ja) * 1991-08-09 1993-02-26 Fujitsu Ltd 出力回路
JPH08102194A (ja) * 1994-09-30 1996-04-16 Nec Corp 半導体メモリ回路
US7289572B2 (en) 2002-10-07 2007-10-30 International Business Machines Corporation Method and system for scalable pre-driver to driver interface
US8038517B2 (en) 2005-09-13 2011-10-18 Fujitsu General Limited Air conditioner and method for assembling the same
JP2017503303A (ja) * 2014-01-09 2017-01-26 クアルコム，インコーポレイテッド ダイナミックランダムアクセスメモリ（ｄｒａｍ）バックチャネル通信システムおよび方法

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5745623A (en) * 1980-08-29 1982-03-15 Fujitsu Ltd Bidirectional input and output circuit

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5745623A (en) * 1980-08-29 1982-03-15 Fujitsu Ltd Bidirectional input and output circuit

Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58172022A (ja) * 1982-03-29 1983-10-08 インタ−ナシヨナル　ビジネス　マシ−ンズ　コ−ポレ−シヨン 駆動回路
JPS59229923A (ja) * 1983-06-13 1984-12-24 Hitachi Ltd 集積回路用論理回路
JPS59229924A (ja) * 1983-06-13 1984-12-24 Hitachi Ltd 集積回路用論理回路
JPS61212116A (ja) * 1985-03-15 1986-09-20 Nec Corp 半導体集積回路
JPH03142788A (ja) * 1989-10-27 1991-06-18 Nec Corp 半導体メモリ用センスアンプ回路
JPH0547185A (ja) * 1991-08-09 1993-02-26 Fujitsu Ltd 出力回路
JPH08102194A (ja) * 1994-09-30 1996-04-16 Nec Corp 半導体メモリ回路
US7289572B2 (en) 2002-10-07 2007-10-30 International Business Machines Corporation Method and system for scalable pre-driver to driver interface
US8038517B2 (en) 2005-09-13 2011-10-18 Fujitsu General Limited Air conditioner and method for assembling the same
JP2017503303A (ja) * 2014-01-09 2017-01-26 クアルコム，インコーポレイテッド ダイナミックランダムアクセスメモリ（ｄｒａｍ）バックチャネル通信システムおよび方法
US10224081B2 (en) 2014-01-09 2019-03-05 Qualcomm Incorporated Dynamic random access memory (DRAM) backchannel communication systems and methods

Also Published As

Publication number Publication date
JPH0456491B2 (enrdf_load_html_response) 1992-09-08

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