JPS57150178A - Write system for memory - Google Patents

Write system for memory

Info

Publication number
JPS57150178A
JPS57150178A JP3315481A JP3315481A JPS57150178A JP S57150178 A JPS57150178 A JP S57150178A JP 3315481 A JP3315481 A JP 3315481A JP 3315481 A JP3315481 A JP 3315481A JP S57150178 A JPS57150178 A JP S57150178A
Authority
JP
Japan
Prior art keywords
chip
memory
signal
register
chips
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3315481A
Other languages
Japanese (ja)
Inventor
Katsuhiro Oki
Naoki Yamazaki
Mamiko Nakamura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP3315481A priority Critical patent/JPS57150178A/en
Publication of JPS57150178A publication Critical patent/JPS57150178A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/20—Memory cell initialisation circuits, e.g. when powering up or down, memory clear, latent image memory

Abstract

PURPOSE:To achieve clear operation in a short time, by providing a programmable register and obtaining a signal of chip individual selection or chip full selection, in a write operation to a memory consisting of a plurality of chips. CONSTITUTION:A memory MEM consists of a plurality of chips CP1, CP2... and is provided with chip selecting terminals SEL1, SEL2.... A programmable register PGR enables an output signals to be suitably programmed with a control signal from an address bus ADB. For example, when a prescribed control signal is inputted, and when output signals of a register all go to 1 and are applied to the terminals SEL1, SEL2..., if a signal on the data bus ADB is zero, all zero is written in a memory quickly. A register PGR is controlled to select a chip with a prescribed pattern and a signal on the bus DB goes to 1, then 1 is wirtten in a selected chip. Thus, the same signal is written in all the chips of the memory in a short time.
JP3315481A 1981-03-10 1981-03-10 Write system for memory Pending JPS57150178A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3315481A JPS57150178A (en) 1981-03-10 1981-03-10 Write system for memory

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3315481A JPS57150178A (en) 1981-03-10 1981-03-10 Write system for memory

Publications (1)

Publication Number Publication Date
JPS57150178A true JPS57150178A (en) 1982-09-16

Family

ID=12378649

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3315481A Pending JPS57150178A (en) 1981-03-10 1981-03-10 Write system for memory

Country Status (1)

Country Link
JP (1) JPS57150178A (en)

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