JPS57205897A - Memory access controller - Google Patents

Memory access controller

Info

Publication number
JPS57205897A
JPS57205897A JP56088840A JP8884081A JPS57205897A JP S57205897 A JPS57205897 A JP S57205897A JP 56088840 A JP56088840 A JP 56088840A JP 8884081 A JP8884081 A JP 8884081A JP S57205897 A JPS57205897 A JP S57205897A
Authority
JP
Japan
Prior art keywords
memory
register
writing
time
memory access
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP56088840A
Other languages
Japanese (ja)
Inventor
Terukazu Kito
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Oki Electric Industry Co Ltd
Original Assignee
Oki Electric Industry Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Oki Electric Industry Co Ltd filed Critical Oki Electric Industry Co Ltd
Priority to JP56088840A priority Critical patent/JPS57205897A/en
Publication of JPS57205897A publication Critical patent/JPS57205897A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/18—Address generation devices; Devices for accessing memories, e.g. details of addressing circuits
    • G11C29/26—Accessing multiple arrays
    • G11C29/28—Dependent multiple arrays, e.g. multi-bit arrays

Landscapes

  • Techniques For Improving Reliability Of Storages (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)

Abstract

PURPOSE:To sharply reduce the accessing time, by simultaneously accessing plural memory chips at the time of writing, and accessing the memory after returning to the conventional memory space at the time of writing and readout of a specified pattern. CONSTITUTION:When a memory access signal and a memory write signal are inputted into a 3AND under condition where a flip flop FF is set, all of outputs of 16 pieces of off circuits OR1-OR16 become ''1'' and all memories are selected. Then, a fixed pattern is set to the 1st register R1 and the same fixed pattern is set to a data register Rd from the register R1. When the writing operation is executed by setting the 16383 to an address register Ra and delivering the memory access signal and memory write signal from a memory controller, the writing operation is executed on all memories of the memory.
JP56088840A 1981-06-11 1981-06-11 Memory access controller Pending JPS57205897A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56088840A JPS57205897A (en) 1981-06-11 1981-06-11 Memory access controller

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56088840A JPS57205897A (en) 1981-06-11 1981-06-11 Memory access controller

Publications (1)

Publication Number Publication Date
JPS57205897A true JPS57205897A (en) 1982-12-17

Family

ID=13954151

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56088840A Pending JPS57205897A (en) 1981-06-11 1981-06-11 Memory access controller

Country Status (1)

Country Link
JP (1) JPS57205897A (en)

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