JPS57146338A - Data separation buffering system - Google Patents

Data separation buffering system

Info

Publication number
JPS57146338A
JPS57146338A JP56030717A JP3071781A JPS57146338A JP S57146338 A JPS57146338 A JP S57146338A JP 56030717 A JP56030717 A JP 56030717A JP 3071781 A JP3071781 A JP 3071781A JP S57146338 A JPS57146338 A JP S57146338A
Authority
JP
Japan
Prior art keywords
transmission
bus
control
picture signal
section
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP56030717A
Other languages
Japanese (ja)
Inventor
Kunio Fukuhara
Mitsuo Nishida
Naoaki Adachi
Yukima Suzuki
Tamio Ito
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
NEC Corp
Nippon Telegraph and Telephone Corp
Original Assignee
Fujitsu Ltd
NEC Corp
Nippon Telegraph and Telephone Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd, NEC Corp, Nippon Telegraph and Telephone Corp, Nippon Electric Co Ltd filed Critical Fujitsu Ltd
Priority to JP56030717A priority Critical patent/JPS57146338A/en
Publication of JPS57146338A publication Critical patent/JPS57146338A/en
Pending legal-status Critical Current

Links

Landscapes

  • Computer And Data Communications (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)

Abstract

PURPOSE: To achieve transmission of a lot of data, by providing a memory section of a control signal directly accessible from a processor and that of a data signal not accessed directly from the processor, in a data transmission controller of a storage exchange system.
CONSTITUTION: Signals on a transmission line consisting of control signals C0W Cn and facsimile picture signals P0WPm are separated into A and B at a line unit 4, and when a multiple transmission control section 5 receives the instruction of reception from a 8-bit microprocessor (MPU) 6 via a bus 7, a control signal is written in a memory 8 from a designated address, and a picture signal is written in a buffer memory section 10 via a bus 9. The MPU 6 gives a transmission instruction to a control interface 11 and the control is given to a central processing device 1 via a bus 102. The picture signal transmits a transmission address to a picture signal interface section 12 via the bus 7 with the transmission request from the device 1 through arrangement in transmission unit and the address is transmitted to the device 1 from a memory 8 through the picture signal interface 12 and a bus 103.
COPYRIGHT: (C)1982,JPO&Japio
JP56030717A 1981-03-04 1981-03-04 Data separation buffering system Pending JPS57146338A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56030717A JPS57146338A (en) 1981-03-04 1981-03-04 Data separation buffering system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56030717A JPS57146338A (en) 1981-03-04 1981-03-04 Data separation buffering system

Publications (1)

Publication Number Publication Date
JPS57146338A true JPS57146338A (en) 1982-09-09

Family

ID=12311391

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56030717A Pending JPS57146338A (en) 1981-03-04 1981-03-04 Data separation buffering system

Country Status (1)

Country Link
JP (1) JPS57146338A (en)

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