JPS57145470A - Signal processor - Google Patents
Signal processorInfo
- Publication number
- JPS57145470A JPS57145470A JP56030753A JP3075381A JPS57145470A JP S57145470 A JPS57145470 A JP S57145470A JP 56030753 A JP56030753 A JP 56030753A JP 3075381 A JP3075381 A JP 3075381A JP S57145470 A JPS57145470 A JP S57145470A
- Authority
- JP
- Japan
- Prior art keywords
- signal
- picture signal
- line
- stored
- group
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N1/00—Scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission; Details thereof
- H04N1/40—Picture signal circuits
- H04N1/409—Edge or detail enhancement; Noise or error suppression
Landscapes
- Engineering & Computer Science (AREA)
- Multimedia (AREA)
- Signal Processing (AREA)
- Image Input (AREA)
- Image Processing (AREA)
- Facsimile Scanning Arrangements (AREA)
- Facsimile Image Signal Circuits (AREA)
Abstract
PURPOSE:To compensate missing of bits of a picture signal which is read with an image sensor, etc. and to obtain a faithful data, by forming an OR alternately the picture signals of two lines by means of two OR circuits and a storage element group. CONSTITUTION:An n-th line picture signal A is supplied and stored in a storage element group 11 by a control signal G. With application of the (n+1)-th line picture signal A, the group 11 is set in the writing mode with a storage element group 12 set in the reading mode respectively. In this connection, the recirculation of the picture signal is inhibited to an OR circuit 15 by a control signal H. After this, the signal A is written into the groups 11 and 12, the signal of n+(n+1) is produced by an OR circuit 14 and stored for the group 11. At the same time, a picture signal C obtained from the (n-1)-th line and n-th line signals through an OR and stored in the element 12 is supplied to a selecting circuit 13, and the (n+1)-th line picture signal A is stored simultaneously. After this, the same actions are repeated alternately.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP56030753A JPS57145470A (en) | 1981-03-03 | 1981-03-03 | Signal processor |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP56030753A JPS57145470A (en) | 1981-03-03 | 1981-03-03 | Signal processor |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS57145470A true JPS57145470A (en) | 1982-09-08 |
JPH0313784B2 JPH0313784B2 (en) | 1991-02-25 |
Family
ID=12312436
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP56030753A Granted JPS57145470A (en) | 1981-03-03 | 1981-03-03 | Signal processor |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS57145470A (en) |
-
1981
- 1981-03-03 JP JP56030753A patent/JPS57145470A/en active Granted
Also Published As
Publication number | Publication date |
---|---|
JPH0313784B2 (en) | 1991-02-25 |
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