JPS5714215A - Stabilizing circuit for a/d converter - Google Patents

Stabilizing circuit for a/d converter

Info

Publication number
JPS5714215A
JPS5714215A JP8890180A JP8890180A JPS5714215A JP S5714215 A JPS5714215 A JP S5714215A JP 8890180 A JP8890180 A JP 8890180A JP 8890180 A JP8890180 A JP 8890180A JP S5714215 A JPS5714215 A JP S5714215A
Authority
JP
Japan
Prior art keywords
digital
signal
output
converter
adder
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP8890180A
Other languages
Japanese (ja)
Other versions
JPS6239850B2 (en
Inventor
Kenjiro Endo
Yoshiyuki Ishizawa
Masanori Tanaka
Koji Iwasaki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
EMI Records Japan Inc
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Toshiba Emi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd, Toshiba Emi Ltd filed Critical Toshiba Corp
Priority to JP8890180A priority Critical patent/JPS5714215A/en
Publication of JPS5714215A publication Critical patent/JPS5714215A/en
Publication of JPS6239850B2 publication Critical patent/JPS6239850B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/06—Continuously compensating for, or preventing, undesired influence of physical parameters

Abstract

PURPOSE:To correct the step response delay and waveform distortion of an AD conversion output stabilized by positive feedback, by a feed forward type correcting means of performing delay adding processing. CONSTITUTION:An analog input signal (x) after passing through a coefficient device 11 is added by an adder 12 to a feedback signal and the resulting sum is supplied to an AD converter 13. The one-sampling-period delay output of a digital signal outputted via a latch circuit 14 is partially fed back as the said feedback signal, and the remainder is supplied to an adder 18 via a digital coefficient device 17. The digital coefficient device 17 multiplies the digital signal inputted in parallel by coefficient 0.5 by shifting it by one bit, and the adder 18 addes the output of the digital coefficient device 17 to the digital output signal of the AD converter 13 to obtain the digital conversion output of the stabilized analog input signal (x).
JP8890180A 1980-06-30 1980-06-30 Stabilizing circuit for a/d converter Granted JPS5714215A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8890180A JPS5714215A (en) 1980-06-30 1980-06-30 Stabilizing circuit for a/d converter

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8890180A JPS5714215A (en) 1980-06-30 1980-06-30 Stabilizing circuit for a/d converter

Publications (2)

Publication Number Publication Date
JPS5714215A true JPS5714215A (en) 1982-01-25
JPS6239850B2 JPS6239850B2 (en) 1987-08-25

Family

ID=13955849

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8890180A Granted JPS5714215A (en) 1980-06-30 1980-06-30 Stabilizing circuit for a/d converter

Country Status (1)

Country Link
JP (1) JPS5714215A (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0379826U (en) * 1989-12-01 1991-08-15

Also Published As

Publication number Publication date
JPS6239850B2 (en) 1987-08-25

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