JPS57141132A - Misfet logical circuit with depletion type load transistor - Google Patents
Misfet logical circuit with depletion type load transistorInfo
- Publication number
- JPS57141132A JPS57141132A JP56189342A JP18934281A JPS57141132A JP S57141132 A JPS57141132 A JP S57141132A JP 56189342 A JP56189342 A JP 56189342A JP 18934281 A JP18934281 A JP 18934281A JP S57141132 A JPS57141132 A JP S57141132A
- Authority
- JP
- Japan
- Prior art keywords
- load transistor
- block
- current
- misfet
- fets
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/0008—Arrangements for reducing power consumption
- H03K19/0013—Arrangements for reducing power consumption in field effect transistor circuits
Landscapes
- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Computing Systems (AREA)
- General Engineering & Computer Science (AREA)
- Mathematical Physics (AREA)
- Logic Circuits (AREA)
Abstract
PURPOSE:To reduce power consumption by reducing the mean amount of a current by adding MISFETs to a logical block. CONSTITUTION:A deletion type MISFETQl1 wherein a current flows between its source and drain even if no bias voltage is applied between its gate and source is used as a load transistor (TR), and enhancement type MISFETs Qd1-Qd3 wherein currents flow between their sources and drains when bias voltages are applied are used as driving TRs; and an MISFETQd4 applied with a clock pulse phi at its gate electrode is added, and the FETs Ql1 and Qd4 and a logical block LB are connected in series, so that an output signal appears at the connection point of the block LB and FETQl1. Then, only when the FETQd4 turns on by the clock pulse phi, a current flows through the series closed loop of the FETs Ql1 and Qd4, and the block LB, and the current does not flow normally, reducing power consumption.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP56189342A JPS57141132A (en) | 1981-11-27 | 1981-11-27 | Misfet logical circuit with depletion type load transistor |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP56189342A JPS57141132A (en) | 1981-11-27 | 1981-11-27 | Misfet logical circuit with depletion type load transistor |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP47084565A Division JPS5931253B2 (en) | 1972-08-25 | 1972-08-25 | MISFET logic circuit with depletion type load transistor |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS57141132A true JPS57141132A (en) | 1982-09-01 |
Family
ID=16239726
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP56189342A Pending JPS57141132A (en) | 1981-11-27 | 1981-11-27 | Misfet logical circuit with depletion type load transistor |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS57141132A (en) |
-
1981
- 1981-11-27 JP JP56189342A patent/JPS57141132A/en active Pending
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