JPS57136810A - Frequency modulating system using pll - Google Patents

Frequency modulating system using pll

Info

Publication number
JPS57136810A
JPS57136810A JP56022842A JP2284281A JPS57136810A JP S57136810 A JPS57136810 A JP S57136810A JP 56022842 A JP56022842 A JP 56022842A JP 2284281 A JP2284281 A JP 2284281A JP S57136810 A JPS57136810 A JP S57136810A
Authority
JP
Japan
Prior art keywords
properties
frequency
pll
modulation
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP56022842A
Other languages
Japanese (ja)
Other versions
JPS6316922B2 (en
Inventor
Kazuo Yamashita
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Japan Radio Co Ltd
Nihon Musen KK
Original Assignee
Japan Radio Co Ltd
Nihon Musen KK
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Japan Radio Co Ltd, Nihon Musen KK filed Critical Japan Radio Co Ltd
Priority to JP56022842A priority Critical patent/JPS57136810A/en
Publication of JPS57136810A publication Critical patent/JPS57136810A/en
Publication of JPS6316922B2 publication Critical patent/JPS6316922B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03C—MODULATION
    • H03C3/00—Angle modulation
    • H03C3/02—Details
    • H03C3/09—Modifications of modulator for regulating the mean frequency
    • H03C3/0908—Modifications of modulator for regulating the mean frequency using a phase locked loop
    • H03C3/0975—Modifications of modulator for regulating the mean frequency using a phase locked loop applying frequency modulation in the phase locked loop at components other than the divider, the voltage controlled oscillator or the reference clock
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03C—MODULATION
    • H03C3/00—Angle modulation
    • H03C3/02—Details
    • H03C3/09—Modifications of modulator for regulating the mean frequency
    • H03C3/0908—Modifications of modulator for regulating the mean frequency using a phase locked loop
    • H03C3/0941—Modifications of modulator for regulating the mean frequency using a phase locked loop applying frequency modulation at more than one point in the loop
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03C—MODULATION
    • H03C3/00—Angle modulation
    • H03C3/02—Details
    • H03C3/09—Modifications of modulator for regulating the mean frequency
    • H03C3/0908—Modifications of modulator for regulating the mean frequency using a phase locked loop
    • H03C3/0958—Modifications of modulator for regulating the mean frequency using a phase locked loop applying frequency modulation by varying the characteristics of the voltage controlled oscillator
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03C—MODULATION
    • H03C2200/00—Indexing scheme relating to details of modulators or modulation methods covered by H03C
    • H03C2200/0037—Functional aspects of modulators
    • H03C2200/005—Modulation sensitivity
    • H03C2200/0054—Filtering of the input modulating signal for obtaining a constant sensitivity of frequency modulation

Landscapes

  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
  • Digital Transmission Methods That Use Modulated Carrier Waves (AREA)

Abstract

PURPOSE:To realize the modulation of frequency regardless of the frequency response properties of a PLL, by receiving an integral output from an integral network as well as an output from a phase wave detecting circuit and adding these outputs together to feed them to a filter circuit. CONSTITUTION:The conventional modulation properties can be obtained through a negative feedback loop which returns to a voltage-frequency converting circuit 2 via a divider 4, a phase wave detecting circuit 5, an adder circuit 8 and an active filter 7, respectively. On the other hand, the modulated signal applied to an input terminal 1 is integrated through an integral network 9. In this case, the modulation properties is proportional to the response properties of a conventional PLL. Accordingly, a flat modulation properties can be obtained over a low to high range of the modulated frequency by adding 8 the modulated signals in a specific level relation.
JP56022842A 1981-02-18 1981-02-18 Frequency modulating system using pll Granted JPS57136810A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56022842A JPS57136810A (en) 1981-02-18 1981-02-18 Frequency modulating system using pll

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56022842A JPS57136810A (en) 1981-02-18 1981-02-18 Frequency modulating system using pll

Publications (2)

Publication Number Publication Date
JPS57136810A true JPS57136810A (en) 1982-08-24
JPS6316922B2 JPS6316922B2 (en) 1988-04-12

Family

ID=12093956

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56022842A Granted JPS57136810A (en) 1981-02-18 1981-02-18 Frequency modulating system using pll

Country Status (1)

Country Link
JP (1) JPS57136810A (en)

Also Published As

Publication number Publication date
JPS6316922B2 (en) 1988-04-12

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