JPS57132363A - Semiconductor device and manufacture thereof - Google Patents

Semiconductor device and manufacture thereof

Info

Publication number
JPS57132363A
JPS57132363A JP56017256A JP1725681A JPS57132363A JP S57132363 A JPS57132363 A JP S57132363A JP 56017256 A JP56017256 A JP 56017256A JP 1725681 A JP1725681 A JP 1725681A JP S57132363 A JPS57132363 A JP S57132363A
Authority
JP
Japan
Prior art keywords
regions
type semiconductor
layer
film
windows
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP56017256A
Other languages
Japanese (ja)
Inventor
Shigeru Kawamura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Faurecia Clarion Electronics Co Ltd
Original Assignee
Clarion Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Clarion Co Ltd filed Critical Clarion Co Ltd
Priority to JP56017256A priority Critical patent/JPS57132363A/en
Publication of JPS57132363A publication Critical patent/JPS57132363A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Junction Field-Effect Transistors (AREA)

Abstract

PURPOSE:To simplify the manufacture of the FET with two gate systems for the subject semiconductor device by a method wherein a pair of N<+> type regions are provided on the substrate having a P type semiconductor layer on both surfaces of an N type semiconductor layer, and then an electrode is provided on the surface of the substrate located between both regions. CONSTITUTION:An insulating film 6, consisting of an oxide film, is formed on the surface of the layer 1 of the semiconductor substrate having the first and the second P type semiconductor layers 1 and 5 on the surface through the intermediary of an N type semiconductor layer 4. Then, a pair of windows 11 and 12 are formed by removing the unnecessary part of the film 6, a pair of N<+> type semiconductor regions 2 and 3 are formed by performing a diffusion process until the N type impurities reach the layer 4, and at the same time, an oxide film is regrown on the surface of the windows 11 and 12. Then, an insulating film 6A is obtained by performing etching on the oxide film on the surface of the layer 1 between the regions 2 and 3. Subsequently, after windows 13 and 14 have been formed by removing the film 6 on the surface of the regions 2 and 3, the unnecessary part is removed by evaporating an electrode material on the whole surface, and electrodes 7-9 are formed. Also, an electrode 10 is formed on the reverse side. And the regions 2 and 3 are jointly used as the drain and source of a J-FET and an MISFET.
JP56017256A 1981-02-06 1981-02-06 Semiconductor device and manufacture thereof Pending JPS57132363A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56017256A JPS57132363A (en) 1981-02-06 1981-02-06 Semiconductor device and manufacture thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56017256A JPS57132363A (en) 1981-02-06 1981-02-06 Semiconductor device and manufacture thereof

Publications (1)

Publication Number Publication Date
JPS57132363A true JPS57132363A (en) 1982-08-16

Family

ID=11938873

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56017256A Pending JPS57132363A (en) 1981-02-06 1981-02-06 Semiconductor device and manufacture thereof

Country Status (1)

Country Link
JP (1) JPS57132363A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006086549A (en) * 2005-12-12 2006-03-30 Nissan Motor Co Ltd Field effect transistor and its manufacturing method
JP2006086548A (en) * 2005-12-12 2006-03-30 Nissan Motor Co Ltd Field effect transistor

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006086549A (en) * 2005-12-12 2006-03-30 Nissan Motor Co Ltd Field effect transistor and its manufacturing method
JP2006086548A (en) * 2005-12-12 2006-03-30 Nissan Motor Co Ltd Field effect transistor

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