JPS57132346A - Resin sealing type semiconductor device - Google Patents

Resin sealing type semiconductor device

Info

Publication number
JPS57132346A
JPS57132346A JP56209256A JP20925681A JPS57132346A JP S57132346 A JPS57132346 A JP S57132346A JP 56209256 A JP56209256 A JP 56209256A JP 20925681 A JP20925681 A JP 20925681A JP S57132346 A JPS57132346 A JP S57132346A
Authority
JP
Japan
Prior art keywords
section
leads
mounting
lead
plated
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP56209256A
Other languages
Japanese (ja)
Inventor
Hiroshi Ozaki
Usuke Enomoto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP56209256A priority Critical patent/JPS57132346A/en
Publication of JPS57132346A publication Critical patent/JPS57132346A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49579—Lead-frames or other flat leads characterised by the materials of the lead frames or layers thereon
    • H01L23/49582—Metallic layers on lead frames
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Abstract

PURPOSE:To prevent a short circuit between lead electrodes by obviating plating to the boundary section with a resin sealing body of a lead member, the upper and lower surfaces of a mounting section thereof for a semiconductor element, etc. are plated. CONSTITUTION:The lead 6 with the semiconductor element mounting section 7 and leads 8 with wire mounting sections 9 are formed by lead frames, the semiconductor element 15 is fixed to the mounting section 7, an element electrode section is connected to the mounting sections 9 by wires 16, and the semiconductor device is shaped through molding by resin 17. The mounting sections 7, 9 of the leads 6, 8 and the upper and lower surfaces of external leads 19 are plated with silver, but the boundary sections 10 with the molding section 17 of the leads 6, 8 are not plated with silver, and copper as the base metal of the lead frames is exposed in the section. A short circuit is not generated between the leads because copper as the base metal is difficult to be dissolved even when a water film layer is shaped to the surface of the molding section.
JP56209256A 1981-12-25 1981-12-25 Resin sealing type semiconductor device Pending JPS57132346A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56209256A JPS57132346A (en) 1981-12-25 1981-12-25 Resin sealing type semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56209256A JPS57132346A (en) 1981-12-25 1981-12-25 Resin sealing type semiconductor device

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
JP10117973A Division JPS5613026B2 (en) 1973-09-10 1973-09-10

Publications (1)

Publication Number Publication Date
JPS57132346A true JPS57132346A (en) 1982-08-16

Family

ID=16569938

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56209256A Pending JPS57132346A (en) 1981-12-25 1981-12-25 Resin sealing type semiconductor device

Country Status (1)

Country Link
JP (1) JPS57132346A (en)

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