JPS5613026B2 - - Google Patents

Info

Publication number
JPS5613026B2
JPS5613026B2 JP10117973A JP10117973A JPS5613026B2 JP S5613026 B2 JPS5613026 B2 JP S5613026B2 JP 10117973 A JP10117973 A JP 10117973A JP 10117973 A JP10117973 A JP 10117973A JP S5613026 B2 JPS5613026 B2 JP S5613026B2
Authority
JP
Japan
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP10117973A
Other languages
Japanese (ja)
Other versions
JPS5052980A (en
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP10117973A priority Critical patent/JPS5613026B2/ja
Publication of JPS5052980A publication Critical patent/JPS5052980A/ja
Publication of JPS5613026B2 publication Critical patent/JPS5613026B2/ja
Expired legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93Batch processes
    • H01L24/95Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
JP10117973A 1973-09-10 1973-09-10 Expired JPS5613026B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10117973A JPS5613026B2 (en) 1973-09-10 1973-09-10

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10117973A JPS5613026B2 (en) 1973-09-10 1973-09-10

Related Child Applications (1)

Application Number Title Priority Date Filing Date
JP56209256A Division JPS57132346A (en) 1981-12-25 1981-12-25 Resin sealing type semiconductor device

Publications (2)

Publication Number Publication Date
JPS5052980A JPS5052980A (en) 1975-05-10
JPS5613026B2 true JPS5613026B2 (en) 1981-03-25

Family

ID=14293756

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10117973A Expired JPS5613026B2 (en) 1973-09-10 1973-09-10

Country Status (1)

Country Link
JP (1) JPS5613026B2 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS51128502A (en) * 1975-04-30 1976-11-09 Matsushita Electric Ind Co Ltd 4-channel headphone unit

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4896075A (en) * 1972-03-21 1973-12-08

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4896075A (en) * 1972-03-21 1973-12-08

Also Published As

Publication number Publication date
JPS5052980A (en) 1975-05-10

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