JPS57126133A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS57126133A
JPS57126133A JP1138181A JP1138181A JPS57126133A JP S57126133 A JPS57126133 A JP S57126133A JP 1138181 A JP1138181 A JP 1138181A JP 1138181 A JP1138181 A JP 1138181A JP S57126133 A JPS57126133 A JP S57126133A
Authority
JP
Japan
Prior art keywords
layer
substrate
approximately
epitaxial
evaporated
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1138181A
Other languages
Japanese (ja)
Inventor
Shuzo Ito
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Home Electronics Ltd
NEC Corp
Original Assignee
NEC Home Electronics Ltd
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Home Electronics Ltd, Nippon Electric Co Ltd filed Critical NEC Home Electronics Ltd
Priority to JP1138181A priority Critical patent/JPS57126133A/en
Publication of JPS57126133A publication Critical patent/JPS57126133A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
    • H01L23/4827—Materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04026—Bonding areas specifically adapted for layer connectors

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

PURPOSE:To obtain an ohmic electrode proper to an epitaxial tpe element by successively forming a metal layer containing the same conduction type impurity, a Cr layer, a Ni layer and a metal layer selected from Ag, Sn, Au onto a semiconductor substrate sequentially through evaporation and thermally treating them. CONSTITUTION:The Au/Sb(0.1-2%) layer 15 is resistance-evaporated to the back side of the N<+> substrate 1 (approximately 5X10<18>cm<-3> Sb concentration) to which an NPN transistor is shaped through the growth of an N<-> epitaxial layer. The Cr layer 16, the Ni layer 17 and the metal layers such as a Sn layer 181 and a Ag layer 182 are evaporated successively onto the layer 15 through heating by electron beams. The while is heated at approximately 400 deg.C in vacuum or an inert atmosphere, and an Au/Si alloy layer 19 is formed while the alloy layer 19 and the Cr layer 16 are fast stuck with each other. Accordingly, the collector electrode, which has excellent ohmic contact, and closely adheres strongly to the substrate and adhesive property thereof by solder is superior, can be shaped.
JP1138181A 1981-01-27 1981-01-27 Manufacture of semiconductor device Pending JPS57126133A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1138181A JPS57126133A (en) 1981-01-27 1981-01-27 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1138181A JPS57126133A (en) 1981-01-27 1981-01-27 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS57126133A true JPS57126133A (en) 1982-08-05

Family

ID=11776428

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1138181A Pending JPS57126133A (en) 1981-01-27 1981-01-27 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS57126133A (en)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS518871A (en) * 1974-07-10 1976-01-24 Hitachi Ltd Handotaisochino denkyoku
JPS5245364B2 (en) * 1972-10-14 1977-11-15
JPS5588324A (en) * 1978-12-27 1980-07-04 Nec Home Electronics Ltd Manufacture of semiconductor ohmic layer

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5245364B2 (en) * 1972-10-14 1977-11-15
JPS518871A (en) * 1974-07-10 1976-01-24 Hitachi Ltd Handotaisochino denkyoku
JPS5588324A (en) * 1978-12-27 1980-07-04 Nec Home Electronics Ltd Manufacture of semiconductor ohmic layer

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