JPS57125435A - System for communication control - Google Patents

System for communication control

Info

Publication number
JPS57125435A
JPS57125435A JP56010651A JP1065181A JPS57125435A JP S57125435 A JPS57125435 A JP S57125435A JP 56010651 A JP56010651 A JP 56010651A JP 1065181 A JP1065181 A JP 1065181A JP S57125435 A JPS57125435 A JP S57125435A
Authority
JP
Japan
Prior art keywords
interruption
control part
indication flag
interrupted
communication control
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP56010651A
Other languages
English (en)
Japanese (ja)
Other versions
JPS6231389B2 (enExample
Inventor
Yoshiharu Tobe
Tatsuo Ushiki
Yoshio Kuboyama
Tsunehachi Ishitani
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NTT Inc
Original Assignee
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Telegraph and Telephone Corp filed Critical Nippon Telegraph and Telephone Corp
Priority to JP56010651A priority Critical patent/JPS57125435A/ja
Publication of JPS57125435A publication Critical patent/JPS57125435A/ja
Publication of JPS6231389B2 publication Critical patent/JPS6231389B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal
    • G06F13/285—Halt processor DMA

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer And Data Communications (AREA)
  • Communication Control (AREA)
JP56010651A 1981-01-27 1981-01-27 System for communication control Granted JPS57125435A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56010651A JPS57125435A (en) 1981-01-27 1981-01-27 System for communication control

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56010651A JPS57125435A (en) 1981-01-27 1981-01-27 System for communication control

Publications (2)

Publication Number Publication Date
JPS57125435A true JPS57125435A (en) 1982-08-04
JPS6231389B2 JPS6231389B2 (enExample) 1987-07-08

Family

ID=11756119

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56010651A Granted JPS57125435A (en) 1981-01-27 1981-01-27 System for communication control

Country Status (1)

Country Link
JP (1) JPS57125435A (enExample)

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
PANAFACOM UýÞ-þ´ ¸-n´cda=S53 *

Also Published As

Publication number Publication date
JPS6231389B2 (enExample) 1987-07-08

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