JPS57122542A - Electrode structure for semiconductor element - Google Patents

Electrode structure for semiconductor element

Info

Publication number
JPS57122542A
JPS57122542A JP56007944A JP794481A JPS57122542A JP S57122542 A JPS57122542 A JP S57122542A JP 56007944 A JP56007944 A JP 56007944A JP 794481 A JP794481 A JP 794481A JP S57122542 A JPS57122542 A JP S57122542A
Authority
JP
Japan
Prior art keywords
probing
layer
substrate
projected
solder
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP56007944A
Other languages
Japanese (ja)
Inventor
Toru Kawanobe
Keiji Miyamoto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP56007944A priority Critical patent/JPS57122542A/en
Publication of JPS57122542A publication Critical patent/JPS57122542A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10Bump connectors ; Manufacturing methods related thereto
    • H01L24/11Manufacturing methods
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/11Manufacturing methods
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/13099Material
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/14Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H01L2224/1401Structure
    • H01L2224/1403Bump connectors having different sizes, e.g. different diameters, heights or widths
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001Core members of the connector
    • H01L2224/45099Material
    • H01L2224/451Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45117Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/45124Aluminium (Al) as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/00014Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01013Aluminum [Al]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01022Titanium [Ti]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01029Copper [Cu]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013Alloys
    • H01L2924/014Solder alloys

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PURPOSE:To prevent the deformation and the damage of a projected solder electrode due to a probing in a semiconductor element and to increase the reliability of the device by forming a probing pad formed in height lower than the projected electrode separately at the position from the projected electrode at the periphery of a substrate provided with the projected solder electrode. CONSTITUTION:An aluminum wire 14 connected to an element substrate 10 through a window is formed on an insulating film 12 on the substrate 10, and a metallic layer 18 of three layers (Ti-Cu-Ti) connected to the aluminum wire layer 14 through the window of a passivation layer 16. A solder bump 20 is formed on a part of the layer 18 by removing the Ti layer on the upper layer, and a probing solder pad 22 having a height higher than the bump 20 and an area smaller than that is formed in the vicinity of the substrate of the layer 18. When the element is tested for probing, a probing stylus is contacted with the pad 22. In this manner, the deformation and the damage can be eliminated at the bump 20, and the decrease in the reliability of the element due to the probing can be prevented.
JP56007944A 1981-01-23 1981-01-23 Electrode structure for semiconductor element Pending JPS57122542A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56007944A JPS57122542A (en) 1981-01-23 1981-01-23 Electrode structure for semiconductor element

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56007944A JPS57122542A (en) 1981-01-23 1981-01-23 Electrode structure for semiconductor element

Publications (1)

Publication Number Publication Date
JPS57122542A true JPS57122542A (en) 1982-07-30

Family

ID=11679600

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56007944A Pending JPS57122542A (en) 1981-01-23 1981-01-23 Electrode structure for semiconductor element

Country Status (1)

Country Link
JP (1) JPS57122542A (en)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6031244A (en) * 1983-08-01 1985-02-18 Oki Electric Ind Co Ltd Semiconductor device
US5734199A (en) * 1995-12-18 1998-03-31 Matsushita Electric Industrial Co., Ltd. Semiconductor device having improved test electrodes
US5969424A (en) * 1997-03-19 1999-10-19 Fujitsu Limited Semiconductor device with pad structure
US6204074B1 (en) * 1995-01-09 2001-03-20 International Business Machines Corporation Chip design process for wire bond and flip-chip package
US6373143B1 (en) 1998-09-24 2002-04-16 International Business Machines Corporation Integrated circuit having wirebond pads suitable for probing
DE19706983B4 (en) * 1996-02-23 2009-06-18 Denso Corporation, Kariya Surface mounting unit and transducer assemblies using the surface mounting unit

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5230381A (en) * 1975-09-03 1977-03-08 Hitachi Ltd Semiconductor integrating circuit

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5230381A (en) * 1975-09-03 1977-03-08 Hitachi Ltd Semiconductor integrating circuit

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6031244A (en) * 1983-08-01 1985-02-18 Oki Electric Ind Co Ltd Semiconductor device
US6204074B1 (en) * 1995-01-09 2001-03-20 International Business Machines Corporation Chip design process for wire bond and flip-chip package
US5734199A (en) * 1995-12-18 1998-03-31 Matsushita Electric Industrial Co., Ltd. Semiconductor device having improved test electrodes
US5811351A (en) * 1995-12-18 1998-09-22 Matsushita Electric Industrial Co., Ltd. Semiconductor device and method of manufacturing the same
EP0780893A3 (en) * 1995-12-18 1998-09-23 Matsushita Electric Industrial Co., Ltd. Semiconductor device and method of manufacturing the same
DE19706983B4 (en) * 1996-02-23 2009-06-18 Denso Corporation, Kariya Surface mounting unit and transducer assemblies using the surface mounting unit
US5969424A (en) * 1997-03-19 1999-10-19 Fujitsu Limited Semiconductor device with pad structure
US6232147B1 (en) 1997-03-19 2001-05-15 Fujitsu Limited Method for manufacturing semiconductor device with pad structure
US6373143B1 (en) 1998-09-24 2002-04-16 International Business Machines Corporation Integrated circuit having wirebond pads suitable for probing
US6429675B2 (en) 1998-09-24 2002-08-06 International Business Machines Corporation Structure and method for probing wiring bond pads

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