JPS6415954A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS6415954A
JPS6415954A JP17098887A JP17098887A JPS6415954A JP S6415954 A JPS6415954 A JP S6415954A JP 17098887 A JP17098887 A JP 17098887A JP 17098887 A JP17098887 A JP 17098887A JP S6415954 A JPS6415954 A JP S6415954A
Authority
JP
Japan
Prior art keywords
electrode pad
guard ring
film
semiconductor substrate
contact holes
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP17098887A
Other languages
Japanese (ja)
Inventor
Shinya Sugimori
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Renesas Semiconductor Package and Test Solutions Co Ltd
Original Assignee
Hitachi Hokkai Semiconductor Ltd
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Hokkai Semiconductor Ltd, Hitachi Ltd filed Critical Hitachi Hokkai Semiconductor Ltd
Priority to JP17098887A priority Critical patent/JPS6415954A/en
Publication of JPS6415954A publication Critical patent/JPS6415954A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
    • H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
    • H01L2224/02163—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
    • H01L2224/02165—Reinforcing structures
    • H01L2224/02166—Collar structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05617—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/05624—Aluminium [Al] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Wire Bonding (AREA)

Abstract

PURPOSE:To prevent the wire connecting the electrode pad to an external lead from slackening and contacting with the chip edge to cause a short by causing at least the part of the guard ring passing the electrode pad to bypass the lower part of the electrode pad through an insulating film, thereby shortening the wire. CONSTITUTION:In a desired part of a semiconductor substrate 5, a thick field oxide film 6 is formed and a polysilicon wiring 7 is formed. Then, after forming a PSG film 9, an under guard ring 11, a metal conductor layer, is formed in a position in line with an electrode pad 8, and on the upper part thereof an inter-layer insulating film 12 is deposited. In the connecting parts between the electrode pad 8 and the polysilicon wiring 7 and between the under guard ring 11 and a guard ring 10, contact holes 13 are formed to expose the ground. In the position at which the guard ring 10 is formed, the surface of the semiconductor substrate 5 is also exposed. Aluminium is formed and patterned to form the electrode pad 8 and guard ring 11, and electrical connection between the conductors is made via the contact holes 13. A passivation film 14 is formed except for the electrode pad 8.
JP17098887A 1987-07-10 1987-07-10 Semiconductor device Pending JPS6415954A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP17098887A JPS6415954A (en) 1987-07-10 1987-07-10 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP17098887A JPS6415954A (en) 1987-07-10 1987-07-10 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS6415954A true JPS6415954A (en) 1989-01-19

Family

ID=15915041

Family Applications (1)

Application Number Title Priority Date Filing Date
JP17098887A Pending JPS6415954A (en) 1987-07-10 1987-07-10 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS6415954A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2016174089A (en) * 2015-03-17 2016-09-29 セイコーエプソン株式会社 Semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2016174089A (en) * 2015-03-17 2016-09-29 セイコーエプソン株式会社 Semiconductor device

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