JPS57113129A - Communication system in computer device - Google Patents

Communication system in computer device

Info

Publication number
JPS57113129A
JPS57113129A JP18798080A JP18798080A JPS57113129A JP S57113129 A JPS57113129 A JP S57113129A JP 18798080 A JP18798080 A JP 18798080A JP 18798080 A JP18798080 A JP 18798080A JP S57113129 A JPS57113129 A JP S57113129A
Authority
JP
Japan
Prior art keywords
data
shared memory
central processor
display
display device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP18798080A
Other languages
Japanese (ja)
Inventor
Mitsuru Yamauchi
Akisuke Mori
Kiminobu Fujisaki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP18798080A priority Critical patent/JPS57113129A/en
Publication of JPS57113129A publication Critical patent/JPS57113129A/en
Pending legal-status Critical Current

Links

Landscapes

  • Information Transfer Systems (AREA)
  • Digital Computer Display Output (AREA)

Abstract

PURPOSE: To use a shared memory stored with commands, data, status signals, and error status signals for communication between a central processor and a display device.
CONSTITUTION: For writing data A, the logical state of a busy signal 502 showing whether a display device 20 is busy or not is confirmed and when so, a central processor 10 transmits a halt signal 501 to the device 20 to set the input and output part of the device 20 connected to an address line 401, a data line 402, etc., as the input and output part of the device 20 in a high impedance state, thereby writing the data A in a shared memory 40. Then, the device 20 reads the data out of the shared memory 40 after the halt signal 501 is reset, and consequently data A is transferred from the central processor 10 to the display device 20 to display it on a display board 201.
COPYRIGHT: (C)1982,JPO&Japio
JP18798080A 1980-12-29 1980-12-29 Communication system in computer device Pending JPS57113129A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP18798080A JPS57113129A (en) 1980-12-29 1980-12-29 Communication system in computer device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP18798080A JPS57113129A (en) 1980-12-29 1980-12-29 Communication system in computer device

Publications (1)

Publication Number Publication Date
JPS57113129A true JPS57113129A (en) 1982-07-14

Family

ID=16215500

Family Applications (1)

Application Number Title Priority Date Filing Date
JP18798080A Pending JPS57113129A (en) 1980-12-29 1980-12-29 Communication system in computer device

Country Status (1)

Country Link
JP (1) JPS57113129A (en)

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