JPS5597628A - Information processor - Google Patents

Information processor

Info

Publication number
JPS5597628A
JPS5597628A JP512479A JP512479A JPS5597628A JP S5597628 A JPS5597628 A JP S5597628A JP 512479 A JP512479 A JP 512479A JP 512479 A JP512479 A JP 512479A JP S5597628 A JPS5597628 A JP S5597628A
Authority
JP
Japan
Prior art keywords
signal
supplied
information processor
register
data
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP512479A
Other languages
Japanese (ja)
Inventor
Toshinori Otsuka
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP512479A priority Critical patent/JPS5597628A/en
Publication of JPS5597628A publication Critical patent/JPS5597628A/en
Pending legal-status Critical Current

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Abstract

PURPOSE: To enhance the function of the 1-chip information processor by using the external connection terminal (selection terminal) which was used for designation of the register as other control terminal.
CONSTITUTION: When the data which is identical to the data held in address register 13 is transmitted from address bus AB, comparator 14 detects the coincidence signal to make AND gates 15 and 16 active. In this case, if writing signal WR is supplied, the signal WR is supplied to register 12 from gate 16 via signal line 18. And the data sent from other information processor through data bus DB is written. While in case reading signal RD is supplied, the signal RD is supplied to gate circuit 17 via signal line 19 from the output end of gate 15. Thus the data held in register 12 is sent to other information processor via data bus DB.
COPYRIGHT: (C)1980,JPO&Japio
JP512479A 1979-01-19 1979-01-19 Information processor Pending JPS5597628A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP512479A JPS5597628A (en) 1979-01-19 1979-01-19 Information processor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP512479A JPS5597628A (en) 1979-01-19 1979-01-19 Information processor

Publications (1)

Publication Number Publication Date
JPS5597628A true JPS5597628A (en) 1980-07-25

Family

ID=11602559

Family Applications (1)

Application Number Title Priority Date Filing Date
JP512479A Pending JPS5597628A (en) 1979-01-19 1979-01-19 Information processor

Country Status (1)

Country Link
JP (1) JPS5597628A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63150741A (en) * 1986-12-16 1988-06-23 Fujitsu Ltd Supervisory system between host computers

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS519525A (en) * 1974-07-12 1976-01-26 Matsushita Electric Works Ltd KONPYUUTANYUSHUTSURYOKUSETSUZOKUHOSHIKI
JPS5326635A (en) * 1976-08-25 1978-03-11 Hitachi Ltd Setting system for unit address

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS519525A (en) * 1974-07-12 1976-01-26 Matsushita Electric Works Ltd KONPYUUTANYUSHUTSURYOKUSETSUZOKUHOSHIKI
JPS5326635A (en) * 1976-08-25 1978-03-11 Hitachi Ltd Setting system for unit address

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63150741A (en) * 1986-12-16 1988-06-23 Fujitsu Ltd Supervisory system between host computers

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