JPS57111134A - Intersymbol interference compensating circuit - Google Patents
Intersymbol interference compensating circuitInfo
- Publication number
- JPS57111134A JPS57111134A JP18500780A JP18500780A JPS57111134A JP S57111134 A JPS57111134 A JP S57111134A JP 18500780 A JP18500780 A JP 18500780A JP 18500780 A JP18500780 A JP 18500780A JP S57111134 A JPS57111134 A JP S57111134A
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- counter
- counting value
- output
- clock
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L25/00—Baseband systems
- H04L25/38—Synchronous or start-stop systems, e.g. for Baudot code
- H04L25/40—Transmitting circuits; Receiving circuits
Landscapes
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Dc Digital Transmission (AREA)
- Cable Transmission Systems, Equalization Of Radio And Reduction Of Echo (AREA)
Abstract
PURPOSE:To compensate an intersymbol interference by a digital circuit of the same type even if a transmission waveform and a transmission characteristic are different, by changing the number of discrimination and decision in accordance with a result of discrimination of the previous input data. CONSTITUTION:As for input data (a), a high frequency clock (b) and an NOT circuit 6 are brought to AND by an AND circuit 1. A counter 5 is set by a clock signal (c), and counts a high frequency clock of the circuit 1. A counting value deciding circuit 7 makes its output ''0'' in case when an output of a shift register 9 for storing data discriminated before is inputted, and a counting value of the counter 5 does not reach an optimum counting value that has been detected. Also, when said counting value has reached the optimum counting value, ''1'' is outputted, the circuit 1 is closed through the circuit 6, and after that, passing of the clock (b) is inhibited, and the constancy of an output of the counter 5 is held until the next signal (c) is inputted to the counter 5 and the counter 5 is reset. Also, an FF8 shapes a discriminating output of the circuit 7 by the signal (c) and obtains the discriminating output 10 of a binary NRZ code.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP18500780A JPS57111134A (en) | 1980-12-27 | 1980-12-27 | Intersymbol interference compensating circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP18500780A JPS57111134A (en) | 1980-12-27 | 1980-12-27 | Intersymbol interference compensating circuit |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS57111134A true JPS57111134A (en) | 1982-07-10 |
Family
ID=16163138
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP18500780A Pending JPS57111134A (en) | 1980-12-27 | 1980-12-27 | Intersymbol interference compensating circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS57111134A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5957593A (en) * | 1982-09-27 | 1984-04-03 | Nec Corp | Receiving system of calling signal |
-
1980
- 1980-12-27 JP JP18500780A patent/JPS57111134A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5957593A (en) * | 1982-09-27 | 1984-04-03 | Nec Corp | Receiving system of calling signal |
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