JPS5710957A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS5710957A
JPS5710957A JP8602580A JP8602580A JPS5710957A JP S5710957 A JPS5710957 A JP S5710957A JP 8602580 A JP8602580 A JP 8602580A JP 8602580 A JP8602580 A JP 8602580A JP S5710957 A JPS5710957 A JP S5710957A
Authority
JP
Japan
Prior art keywords
main electrode
electrode
upper main
lower main
semiconductor chips
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP8602580A
Other languages
Japanese (ja)
Other versions
JPS6239828B2 (en
Inventor
Hideaki Sannomiya
Yuusaku Morimoto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shindengen Electric Manufacturing Co Ltd
Original Assignee
Shindengen Electric Manufacturing Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shindengen Electric Manufacturing Co Ltd filed Critical Shindengen Electric Manufacturing Co Ltd
Priority to JP8602580A priority Critical patent/JPS5710957A/en
Publication of JPS5710957A publication Critical patent/JPS5710957A/en
Publication of JPS6239828B2 publication Critical patent/JPS6239828B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/07Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00
    • H01L25/072Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00 the devices being arranged next to each other
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484Connecting portions
    • H01L2224/4847Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
    • H01L2224/48472Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/13Discrete devices, e.g. 3 terminal devices
    • H01L2924/1301Thyristor
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191Disposition
    • H01L2924/19101Disposition of discrete passive components
    • H01L2924/19107Disposition of discrete passive components off-chip wires

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Die Bonding (AREA)

Abstract

PURPOSE:To obtain a semiconductor device of large current capacity, by a method wherein a single upper main electrode is secured onto the lower main electrode through an insulating mount, and a plurality of semiconductor chips are conductively secured onto the lower main electrode so as to surround the upper main electrode. CONSTITUTION:An upper main electrode 1 is secured onto a lower main electrode 2 through an insulating mount 3. A plurality of semiconductor chips 5 such as transistors, thyristors or the like are soldered onto the lower main electrode 2 through an electrode plate of molybdenum or the like in an approximate circumference shape with the upper main electrode 1 as a center. A control electrode 7 is provided on the periphery of the arrangement of said semiconductor chips 5 so as to be concentric therewith the upper main electrode 1 as a center. Between the control electrode 7 and the lower main electrode 2, an insulating mount 8 is placed in order to electrically insulate them from each other. Each semiconductor chip 5 and the upper main electrode 1 are connected with a metal wire 6, while each semiconductor chip 5 and the control electrode 7 are connected with a metal wire 9. Thereby, an excellent current balance is obtained among the respective semiconductor chips 5. Accordingly, it is possible to obtain a semiconductor device of large current capacity and without any uneven distribution of heat.
JP8602580A 1980-06-25 1980-06-25 Semiconductor device Granted JPS5710957A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8602580A JPS5710957A (en) 1980-06-25 1980-06-25 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8602580A JPS5710957A (en) 1980-06-25 1980-06-25 Semiconductor device

Publications (2)

Publication Number Publication Date
JPS5710957A true JPS5710957A (en) 1982-01-20
JPS6239828B2 JPS6239828B2 (en) 1987-08-25

Family

ID=13875111

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8602580A Granted JPS5710957A (en) 1980-06-25 1980-06-25 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS5710957A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03130388A (en) * 1989-10-14 1991-06-04 Dowa Mining Co Ltd Plating treatment of metallic blank material of aluminum system

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03130388A (en) * 1989-10-14 1991-06-04 Dowa Mining Co Ltd Plating treatment of metallic blank material of aluminum system

Also Published As

Publication number Publication date
JPS6239828B2 (en) 1987-08-25

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