JPS57109079A - Composite computer system - Google Patents

Composite computer system

Info

Publication number
JPS57109079A
JPS57109079A JP55185931A JP18593180A JPS57109079A JP S57109079 A JPS57109079 A JP S57109079A JP 55185931 A JP55185931 A JP 55185931A JP 18593180 A JP18593180 A JP 18593180A JP S57109079 A JPS57109079 A JP S57109079A
Authority
JP
Japan
Prior art keywords
programs
timers
interruption
computer
update
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP55185931A
Other languages
Japanese (ja)
Inventor
Masaji Aoyama
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP55185931A priority Critical patent/JPS57109079A/en
Publication of JPS57109079A publication Critical patent/JPS57109079A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring

Abstract

PURPOSE:To achieve accurate fault detection by performing the fault detection even while the other computer stops reading/writing operation, by detecting a fault of an interruption generating function by a current status, etc., when interrupting the other computer. CONSTITUTION:Main storage devices 1b and 2b connected to the CPUs 1a and 2a of computers 1 and 2 of a composite computer system are provided with programs 4b and 5b for interruption processing, and monitor processing programs 4a and 5a for an interruption function (CSL). Further, those storage devices 1b and 2b are provided with timers 6a and 7a which update and store the times of the computers 1 and 2 at prescribed itervals of time, monitor processing timers 6b and 7b which copy and update the outputs of the internal times 6a and 7a every time the programs 4a and 5a are executed, and interruption processing timers 6c and 7c which copy and update the outputs of the timers 6a and 7a every time the programs 4b and 5b are ececuted. Then, the programs 4a and 4b are executed in the storage devices 1b and 2b to perform fault detection even while the other computer 1 or 2 stops reading/writing operation.
JP55185931A 1980-12-26 1980-12-26 Composite computer system Pending JPS57109079A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55185931A JPS57109079A (en) 1980-12-26 1980-12-26 Composite computer system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55185931A JPS57109079A (en) 1980-12-26 1980-12-26 Composite computer system

Publications (1)

Publication Number Publication Date
JPS57109079A true JPS57109079A (en) 1982-07-07

Family

ID=16179376

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55185931A Pending JPS57109079A (en) 1980-12-26 1980-12-26 Composite computer system

Country Status (1)

Country Link
JP (1) JPS57109079A (en)

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