JPS5696335A - Computer using microprogram system - Google Patents

Computer using microprogram system

Info

Publication number
JPS5696335A
JPS5696335A JP17256279A JP17256279A JPS5696335A JP S5696335 A JPS5696335 A JP S5696335A JP 17256279 A JP17256279 A JP 17256279A JP 17256279 A JP17256279 A JP 17256279A JP S5696335 A JPS5696335 A JP S5696335A
Authority
JP
Japan
Prior art keywords
microprogram
micro instruction
output
transmission
external
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP17256279A
Other languages
Japanese (ja)
Inventor
Etsuo Kusumoto
Hiroshi Izumi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP17256279A priority Critical patent/JPS5696335A/en
Publication of JPS5696335A publication Critical patent/JPS5696335A/en
Pending legal-status Critical Current

Links

Landscapes

  • Debugging And Monitoring (AREA)

Abstract

PURPOSE: To facilitate checking the microprogram, by causing the microprocessor itself to output all of the microprogram to the external by executing micro instructions.
CONSTITUTION: When the micro instruction for microprogram transmission is written in micro instruction register 6, control circuit 10 for microprogram transmission detects it to inhibit the write of a new micro instruction. Further, program counter value generating circuit 4 is instructed to increase the value of microprogram counter 3 one by one, and execution start of the micro instruction for microprogram transmission is reported to CPU control circuit 8. Thus, contents of microprogram addresses are output from memory 5 to bus 11 and are output to the external in the address order.
COPYRIGHT: (C)1981,JPO&Japio
JP17256279A 1979-12-28 1979-12-28 Computer using microprogram system Pending JPS5696335A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP17256279A JPS5696335A (en) 1979-12-28 1979-12-28 Computer using microprogram system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP17256279A JPS5696335A (en) 1979-12-28 1979-12-28 Computer using microprogram system

Publications (1)

Publication Number Publication Date
JPS5696335A true JPS5696335A (en) 1981-08-04

Family

ID=15944144

Family Applications (1)

Application Number Title Priority Date Filing Date
JP17256279A Pending JPS5696335A (en) 1979-12-28 1979-12-28 Computer using microprogram system

Country Status (1)

Country Link
JP (1) JPS5696335A (en)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS50114139A (en) * 1974-02-15 1975-09-06
JPS51136257A (en) * 1975-05-21 1976-11-25 Nec Corp Copy of stored program
JPS543444A (en) * 1977-06-10 1979-01-11 Hitachi Ltd Error detection system

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS50114139A (en) * 1974-02-15 1975-09-06
JPS51136257A (en) * 1975-05-21 1976-11-25 Nec Corp Copy of stored program
JPS543444A (en) * 1977-06-10 1979-01-11 Hitachi Ltd Error detection system

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