JPS5592947A - Interruption control system for microprogram - Google Patents

Interruption control system for microprogram

Info

Publication number
JPS5592947A
JPS5592947A JP16240878A JP16240878A JPS5592947A JP S5592947 A JPS5592947 A JP S5592947A JP 16240878 A JP16240878 A JP 16240878A JP 16240878 A JP16240878 A JP 16240878A JP S5592947 A JPS5592947 A JP S5592947A
Authority
JP
Japan
Prior art keywords
register
contents
main routine
unit
interruption
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP16240878A
Other languages
Japanese (ja)
Inventor
Tadahiro Wada
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP16240878A priority Critical patent/JPS5592947A/en
Publication of JPS5592947A publication Critical patent/JPS5592947A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To make it possible to execute a previously-fixed subroutine at a high speed by executing each subroutine in response to indication from a timer as if a main routine would be executed.
CONSTITUTION: A main routine and various subroutines are stored in control memory 1 and initial addresses of respective routines are accesses by address information set in control memory address register 2. One timer 10 sends an interruption request at a timing point in time, the interruption request is set in interruption register 11 and control unit 5 is informed of that. Unit 5 stacks the contents of register 2 in stack register 12 and contents of a branch adress register set previously are set in register 2. On the basis of branch-destination address information set in register 2, subroutines are executed and after this execution, unit 5 detects an end instruction via data register 4 to set the contents of register 12 in register 2, thereby restarting the interrupted main routine.
COPYRIGHT: (C)1980,JPO&Japio
JP16240878A 1978-12-29 1978-12-29 Interruption control system for microprogram Pending JPS5592947A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16240878A JPS5592947A (en) 1978-12-29 1978-12-29 Interruption control system for microprogram

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16240878A JPS5592947A (en) 1978-12-29 1978-12-29 Interruption control system for microprogram

Publications (1)

Publication Number Publication Date
JPS5592947A true JPS5592947A (en) 1980-07-14

Family

ID=15754030

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16240878A Pending JPS5592947A (en) 1978-12-29 1978-12-29 Interruption control system for microprogram

Country Status (1)

Country Link
JP (1) JPS5592947A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5500809A (en) * 1992-08-31 1996-03-19 Sharp Kabushiki Kaisha Microcomputer system provided with mechanism for controlling operation of program
US5729727A (en) * 1994-12-06 1998-03-17 Matsushita Electric Industrial Co., Ltd. Pipelined processor which reduces branch instruction interlocks by compensating for misaligned branch instructions

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5500809A (en) * 1992-08-31 1996-03-19 Sharp Kabushiki Kaisha Microcomputer system provided with mechanism for controlling operation of program
US5729727A (en) * 1994-12-06 1998-03-17 Matsushita Electric Industrial Co., Ltd. Pipelined processor which reduces branch instruction interlocks by compensating for misaligned branch instructions
EP0716376A3 (en) * 1994-12-06 1998-04-01 Matsushita Electric Industrial Co., Ltd. A pipeline processor with reduced interlocks caused by branch instructions

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