JPS5694766A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS5694766A JPS5694766A JP17106579A JP17106579A JPS5694766A JP S5694766 A JPS5694766 A JP S5694766A JP 17106579 A JP17106579 A JP 17106579A JP 17106579 A JP17106579 A JP 17106579A JP S5694766 A JPS5694766 A JP S5694766A
- Authority
- JP
- Japan
- Prior art keywords
- type
- area
- emitter
- transistor
- epitaxial layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/082—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including bipolar components only
- H01L27/0821—Combination of lateral and vertical transistors only
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Static Random-Access Memory (AREA)
- Bipolar Transistors (AREA)
- Bipolar Integrated Circuits (AREA)
- Semiconductor Memories (AREA)
Abstract
PURPOSE:To quicken a switching speed as well as to miniaturize a pattern by a method wherein a p type emitter area is formed in a concave part of an n type epitaxial layer in a bipolar memory cell having a pnp transistor load. CONSTITUTION:The surface of an n<-> type epitaxial layer 17 separated by a p<+> type area 27 is formed into a concave face 25 through an etching, and thereafter, a p type impurity diffusion is performed to form an emitter area 15 and a collector area 19 of a pnp type transistor for load. A p<+> type emitter area 15 is formed so as to be in contact with an n<+> embedded layer 26. The above-mentioned n<-> epitaxial layer 17 is a base area of the npn type transistor and is jointly a collector area of the npn type transistor. Thereafter, emitter areas 21, 23 of the npn type transistor are formed. With this, the emitter area 15 reaches an n<+> embedded layer with a comparatively short diffusion distance, accordingly, the occupation pattern of the memory cell can be miniaturized and the operation speed can be also improved.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP54171065A JPS6043030B2 (en) | 1979-12-28 | 1979-12-28 | semiconductor equipment |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP54171065A JPS6043030B2 (en) | 1979-12-28 | 1979-12-28 | semiconductor equipment |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS5694766A true JPS5694766A (en) | 1981-07-31 |
JPS6043030B2 JPS6043030B2 (en) | 1985-09-26 |
Family
ID=15916393
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP54171065A Expired JPS6043030B2 (en) | 1979-12-28 | 1979-12-28 | semiconductor equipment |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6043030B2 (en) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH02311893A (en) * | 1989-05-29 | 1990-12-27 | Hitachi Ltd | High-accuracy pll device |
-
1979
- 1979-12-28 JP JP54171065A patent/JPS6043030B2/en not_active Expired
Also Published As
Publication number | Publication date |
---|---|
JPS6043030B2 (en) | 1985-09-26 |
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