JPS5690496A - Charge input circuit - Google Patents

Charge input circuit

Info

Publication number
JPS5690496A
JPS5690496A JP16882879A JP16882879A JPS5690496A JP S5690496 A JPS5690496 A JP S5690496A JP 16882879 A JP16882879 A JP 16882879A JP 16882879 A JP16882879 A JP 16882879A JP S5690496 A JPS5690496 A JP S5690496A
Authority
JP
Japan
Prior art keywords
amplifier
charge
input terminal
ccd
input circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP16882879A
Other languages
Japanese (ja)
Inventor
Yuichiro Ito
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP16882879A priority Critical patent/JPS5690496A/en
Publication of JPS5690496A publication Critical patent/JPS5690496A/en
Pending legal-status Critical Current

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Abstract

PURPOSE: To perform charge inputting to a CCD accurately by substituting the resistances constituting an operational amplifier, that is, charge input circuit, with switched capacitors.
CONSTITUTION: A charge input circuit 2 for a CCD consisting of a capacitor Ci, a resistance Ri and a power source VB for inputting charge are able to substituted with an operational amplifier OP2' having an input resistance R1 and a feedback resistance R2. Thereupon, known switched capacitors SC1 and SC2 are appropriated for said R1, R2. The output terminal of the amplifier A provided with both positive and negative terminals are connected to the analog signal input part 4a of the CCD, and the switched capacitors SC1 and SC2 consisting of capacitors and switches are connected between the 1st input terminal- and analog signal input terminal 4a of the amplifier A and between the output terminal of the amplifier A and the 1st input terminal-. A DC voltage is applied to the 2nd input terminal of the amplifier A.
COPYRIGHT: (C)1981,JPO&Japio
JP16882879A 1979-12-24 1979-12-24 Charge input circuit Pending JPS5690496A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16882879A JPS5690496A (en) 1979-12-24 1979-12-24 Charge input circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16882879A JPS5690496A (en) 1979-12-24 1979-12-24 Charge input circuit

Publications (1)

Publication Number Publication Date
JPS5690496A true JPS5690496A (en) 1981-07-22

Family

ID=15875263

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16882879A Pending JPS5690496A (en) 1979-12-24 1979-12-24 Charge input circuit

Country Status (1)

Country Link
JP (1) JPS5690496A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008281913A (en) * 2007-05-14 2008-11-20 Toppoly Optoelectronics Corp Display device and pre-charge circuit of the same

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008281913A (en) * 2007-05-14 2008-11-20 Toppoly Optoelectronics Corp Display device and pre-charge circuit of the same
JP4510849B2 (en) * 2007-05-14 2010-07-28 統寶光電股▲ふん▼有限公司 Display device and precharge circuit thereof
TWI415053B (en) * 2007-05-14 2013-11-11 Innolux Corp Display device and pre-charge circuit

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