JPS5681965A - Mos semiconductor integrated circuit - Google Patents

Mos semiconductor integrated circuit

Info

Publication number
JPS5681965A
JPS5681965A JP15897279A JP15897279A JPS5681965A JP S5681965 A JPS5681965 A JP S5681965A JP 15897279 A JP15897279 A JP 15897279A JP 15897279 A JP15897279 A JP 15897279A JP S5681965 A JPS5681965 A JP S5681965A
Authority
JP
Japan
Prior art keywords
line
mos
transistors
transistor
grounding line
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP15897279A
Other languages
Japanese (ja)
Inventor
Sakae Takei
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP15897279A priority Critical patent/JPS5681965A/en
Publication of JPS5681965A publication Critical patent/JPS5681965A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0266—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using field effect transistors as protective elements

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

PURPOSE:To completely protect an MOS element by connecting a sruge absorbing protective element between a power wire for the MOS element and a substrate or between the output wire and the substrate and forming the threshold voltage higher than the using maximum voltage of the MOS element and lower than the P-N junction breakdown voltage. CONSTITUTION:MOS transistors T1 and T2 are connected in series, one region of a transistor T1 is connected to a power line B, the connecting point of the transistors T1 and T2 is connected to an output line O, and the other region of the transistor T2 is connected to the grounding line G. In this configuration a protective element TP1 is connected between the power line B and the grounding line G, and a protective element TP2 is connected between the output line O and the grounding line G. At this time an enhancement MOS transistor is used as the elements TP1 and TP2, the gate and the drain are connected to the power line B, and the source is connected to the grounding line G. Thus, the diode characteristic is provided at the transistors, thereby abruptly reducing the surge to the grounding line G.
JP15897279A 1979-12-07 1979-12-07 Mos semiconductor integrated circuit Pending JPS5681965A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15897279A JPS5681965A (en) 1979-12-07 1979-12-07 Mos semiconductor integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15897279A JPS5681965A (en) 1979-12-07 1979-12-07 Mos semiconductor integrated circuit

Publications (1)

Publication Number Publication Date
JPS5681965A true JPS5681965A (en) 1981-07-04

Family

ID=15683390

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15897279A Pending JPS5681965A (en) 1979-12-07 1979-12-07 Mos semiconductor integrated circuit

Country Status (1)

Country Link
JP (1) JPS5681965A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4578694A (en) * 1981-10-20 1986-03-25 Tokyo Shibaura Denki Kabushiki Kaisha Inverter circuit provided with gate protection

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4578694A (en) * 1981-10-20 1986-03-25 Tokyo Shibaura Denki Kabushiki Kaisha Inverter circuit provided with gate protection

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