JPS5679351A - Memory device - Google Patents

Memory device

Info

Publication number
JPS5679351A
JPS5679351A JP15649179A JP15649179A JPS5679351A JP S5679351 A JPS5679351 A JP S5679351A JP 15649179 A JP15649179 A JP 15649179A JP 15649179 A JP15649179 A JP 15649179A JP S5679351 A JPS5679351 A JP S5679351A
Authority
JP
Japan
Prior art keywords
output
memory
inputs
input
contents
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP15649179A
Other languages
Japanese (ja)
Other versions
JPS6055856B2 (en
Inventor
Tsugio Tawara
Hisanori Hamano
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP54156491A priority Critical patent/JPS6055856B2/en
Publication of JPS5679351A publication Critical patent/JPS5679351A/en
Publication of JPS6055856B2 publication Critical patent/JPS6055856B2/en
Expired legal-status Critical Current

Links

Landscapes

  • Storage Device Security (AREA)

Abstract

PURPOSE:To make it possible to easily executing security of the memory contents, by constituting the device so that a correct output cannot be obtained without inputting the input conforming with the contents stored in the key address memory and the regulation of the comparator. CONSTITUTION:When the electric power source is closed, the one-shot circuit 1 generates a pulse output, sets the FF3, and also outputs pulses for a given period of time from the one-shot circuit 2. Address inputs A0-An are input during said period, and when a chip selective input CS is input, the comparator 5 compares the key address memory 4 with the inputs A0-An, and if they coincide, a signal 1 is output. This output is stored in the shift register 22. An output of the memory 4 is varied when the inputs A0-An are varied, and when the inputs A0-An are input so that they coincide with the contents of the memory 4, the circuit 5 outputs ''1''. Then if all the outputs of the register 22 become ''1'', the FF3 is reset, the output Q' becomes ''1'', and therefore the contents of the memory 6 designated by the inputs A0-An are output to the output lines D0-Dm through the output buffer.
JP54156491A 1979-11-30 1979-11-30 memory device Expired JPS6055856B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP54156491A JPS6055856B2 (en) 1979-11-30 1979-11-30 memory device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP54156491A JPS6055856B2 (en) 1979-11-30 1979-11-30 memory device

Publications (2)

Publication Number Publication Date
JPS5679351A true JPS5679351A (en) 1981-06-29
JPS6055856B2 JPS6055856B2 (en) 1985-12-06

Family

ID=15628910

Family Applications (1)

Application Number Title Priority Date Filing Date
JP54156491A Expired JPS6055856B2 (en) 1979-11-30 1979-11-30 memory device

Country Status (1)

Country Link
JP (1) JPS6055856B2 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01312320A (en) * 1988-06-10 1989-12-18 Matsushita Electric Ind Co Ltd Control device for hot water supply equipment

Also Published As

Publication number Publication date
JPS6055856B2 (en) 1985-12-06

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