JPS6055856B2 - memory device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a memory device whose stored contents are difficult to read independently of a system in which it is incorporated.

As a conventional memory device, there is one shown in FIG.

In the figure, D is an address decoder, M is a memory element group, 7 is an output buffer, 6 is a memory, CS is a chip selection input line, Ao--Am is an address input line, and Dm to Dm are data output lines. Next, the operation will be explained. In a certain system, when reading the contents of a memory, a selection signal is input to the chip selection input line CS to make the selected memory operational, and then input to the address input line M-Am where the data is stored. do. The entered address is
The data is decoded by the address decoder D, predetermined data is read from the memory element group M, and the data is output from the output buffer 7 to the data output lines 1 to Dm. Conventional memory devices are configured as described above, so even if the memory is taken out of the system and used as a standalone memory, data at any address can be easily read out using the same method, making it possible to keep the stored contents confidential. It was difficult to maintain.

The present invention was made in order to eliminate the drawbacks of the conventional devices as described above, and an object of the present invention is to provide a memory device that makes it difficult to read out the stored contents of the memory and makes it possible to maintain confidentiality.

An embodiment of the present invention will be described below with reference to the drawings.

In FIG. 2, 1 is a one-shot circuit that generates a pulse output when the power is turned on; 2 is a one-shot circuit that generates a pulse output for a sawing period based on the output of the one-shot circuit 1;
3 is a set/reset flip-flop, 4 is a key that stores a specific value ●address ●memory (hereinafter referred to as KeyI
l! 4EM. 5 is the period during which the chip selection input is input, KeyMeM. 4 and a comparison circuit that compares the address input, 20 is a KeyMEM. 21 is a binary counter that generates an address to select the contents of memory 6; 21 is a clock signal generation circuit that generates a clock signal when the address changes to select the contents of memory 6 and supplies the clock signal to counter 20; 22 is a comparison circuit. 5 is a shift register that stores the compared results, 8 is an AND gate Al9 is a multi-input AND gate AllO is an AND gate Bll is an output line of one-shot circuit 1, 12 is an output line of one-shot circuit 2, and 13 is a flip-flop. 3 output line, 14 is the output line of multi-input AND gate A9, 15 is AND gate B
AND output line of lO, 23 is clock signal generation circuit 21
30 is the output line of the comparison circuit 5, 31 is the output line of the shift register 22, and 32 is the output line of the AND gate A8. Next, its operation will be explained. When power is applied to the memory, the one-shot circuit 1 generates a pulse output, the flip-flop 3 is set, and the output Q of the flip-flop 3 becomes 660゛1. When the knob selection input is input, the AND gate BIO becomes "0", and the output of the output buffer 7 becomes "0". Further, the output of the one-shot circuit 1 is input to the reset input of the binary counter 20. Binary counter 20 is reset.

Furthermore, the output of the one-shot circuit 1 is input to the one-shot circuit 2, and the one-shot circuit 2 is operated for a certain period (period t).
) A pulse output is output to the output line 12. Details of the circuit 21 that generates a signal when an address changes will be explained with reference to the drawings. FIG. 3 shows an embodiment of the clock signal generation circuit 21, in which 24 is an exclusive OR gate, 25 is a multi-input AND gate, 26 is a capacitive element, 27 is a resistive element, 2
8 is an output line of the signal integrated by the capacitive element 26 and the resistive element 27, and 29 is an output line of the exclusive OR gate 24. The integrated signal of the address input AO-Am is input to one input of the exclusive OR gate 24, and the address input AO-Am is input to the other input.
When Am is input, the address input AO- is sent to the output line 29.
A signal is generated when Am changes. The signal is input to a multi-input AND gate B25, and a clock signal is generated as shown in the timing chart shown in FIG. 4 when an arbitrary address changes. In FIG. 4, a indicates an address input, b an integral signal of the address input, c an output of an exclusive OR gate, and d a clock signal. Due to the above, the second
In the figure, the output of the clock signal generation circuit 21 is Ke
yMEM. It is input to the clock of a binary counter 20 which generates a selection address signal having the contents of 4, and is also input to the clock of a shift register 22 which stores the result of the comparison circuit 5. During the period t during which the pulse output is output from the one-shot circuit 2, a memory address sequence is input to the address input lines AO to Decoration as determined in advance, and when the chip selection input is input, the comparison Circuit 5 is
KeyMEM. Contents stored in 4 and address input AO
-Am is compared according to a predetermined rule, and if they match, a match signal "゜1" is output. This output becomes the data input of the shift register 22, and the shift register is input by the clock input from the clock signal generation circuit 21. Since the clock signal is input to the clock input of the binary counter 20, the address input AO-A
The binary counter 20 counts up when m changes, and K
eyMEM. Since the selection address of 4 changes, the Key
MEM. The output of KeyMEM.4 changes. If you input the address AO-Am so that it matches the contents of 4,
The match signal '6r1 from the sequential comparator circuit 5' is stored in the shift register 22, and when all the outputs of the shift register 22 become '1', the output of the multi-input AND gate A9 becomes '1'.
, the output of the AND gate A8 becomes ``1'', and the flip-flop 3 is reset. When the flip-flop 3 is reset, the output Q of the flip-flop 3 becomes ``1''.
becomes "゜1", and the output of the AND gate BLO also becomes "1", so the contents of the memory 6 specified by the address input AO-Am are transferred via the output buffer 7 to the data output line DO- It is output to Dm. Once the flip-flop 3 is reset by the above operation, the memory 6 can output the data specified by the address input to the data output line DO-Dm no matter what address input is input from now on. Become.

On the other hand, the address input during the period t is KeyMEM
．． 4, the flip-flop 3 is not reset, so the output Q of the flip-flop 3 continues to hold "1".

Therefore, no matter what address is input from now on, the data output line DO-Dm will always be "0", and the correct data output from the memory 6 will not be output to the outside.In addition, in the above example, the flip-flop 3 is reset by the output of one-shot circuit 1, and is reset by the AND output of one-shot circuit 2 and the output of multi-input AND gate A9, but it is reset by the output of one-shot circuit 1, and the one-shot circuit 2 and the output of the multi-input AND gate A9, and the AND output of the output Q of the flip-flop 3 and the chip selection input may be supplied to the output buffer 7.

Alternatively, the one-shot circuit 2 which generates a pulse of period t based on the output of the one-shot circuit 1 may be omitted, and the output of the multi-input AND gate A9 may be directly used as the reset or set input of the flip-flop 3. Alternatively, the flip-flop 3 may be reset or reset from outside the device. As described above, according to the present invention, after power is turned on, a correct output cannot be obtained on the data output line unless an input is input that complies with the contents stored in the key address memory and the rules of the comparison circuit. . Therefore, in order to operate this memory independently from the system and read the contents of the memory, it is necessary to find a key address from the combination of the nod type address input and the memory contents. Because it is very difficult to find
This has the effect of easily maintaining the confidentiality of memory contents.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a conventional memory device, FIG. 2 is a block diagram showing an embodiment of the present invention, FIG. 3 is a circuit diagram showing an embodiment of a clock signal generation circuit, and FIG. 4 is the third
There is a timing chart in the figure. In the figure, 1 and 2 are one-shot circuits, and 3 is a set/
Reset flip-flop, 4 is key●address●memory, 5 is comparison circuit, 6 is memory, . 7 is the output buffer,
8 and 10 are AND gates, 9 is a multi-input AND gate, 2
0 is a binary counter, 21 is a clock signal generation circuit, 22
is a shift register, CS is a chip selection input line, AO-A
m is an address input line, and Dm is a data output line.

Claims (1)

[Claims] 1. A clock signal generation circuit that generates a clock when an address input to a memory changes, a binary counter that counts clocks from this clock signal generation circuit, and an output of this binary counter as an address signal. A key address memory that outputs the contents stored in advance at the address specified by the address signal, a comparison circuit that compares the output of this key address memory and the address input of the memory, and a comparison result of the comparison circuit. A shift register that stores , an AND gate that takes the logical product of the output of this shift register, and a set/reset flip-flop that is reset by the output of this AND gate and sends out an output that controls opening and closing of the output buffer of the memory. A memory device characterized by: 2. A clock signal generation circuit that generates a clock when the address input of the memory changes, a binary counter that counts the clocks from this clock signal generation circuit, and the output of this binary counter as an address signal specified by the address signal. a key address memory that outputs the contents stored in advance at an address, a comparator circuit that compares the output of the key address memory with an address input of the memory, and a shift register that stores the comparison result of the comparator circuit. , an AND gate that ANDs the outputs of this shift register, a set/reset flip-flop that is reset by the output of this AND gate and sends out an output that controls opening and closing of the output buffer of the memory, and a A memory device characterized by comprising: a time limit circuit that enables opening/closing control of an output buffer of the memory.