JPS5674948A - Lead structure of semiconductor device - Google Patents
Lead structure of semiconductor deviceInfo
- Publication number
- JPS5674948A JPS5674948A JP15065479A JP15065479A JPS5674948A JP S5674948 A JPS5674948 A JP S5674948A JP 15065479 A JP15065479 A JP 15065479A JP 15065479 A JP15065479 A JP 15065479A JP S5674948 A JPS5674948 A JP S5674948A
- Authority
- JP
- Japan
- Prior art keywords
- bonded
- tempo
- speed
- bonding operation
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49541—Geometry of the lead-frame
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05554—Shape in top view being square
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Lead Frames For Integrated Circuits (AREA)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP15065479A JPS5674948A (en) | 1979-11-22 | 1979-11-22 | Lead structure of semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP15065479A JPS5674948A (en) | 1979-11-22 | 1979-11-22 | Lead structure of semiconductor device |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS5674948A true JPS5674948A (en) | 1981-06-20 |
JPS6230498B2 JPS6230498B2 (ja) | 1987-07-02 |
Family
ID=15501562
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP15065479A Granted JPS5674948A (en) | 1979-11-22 | 1979-11-22 | Lead structure of semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5674948A (ja) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6281738A (ja) * | 1985-10-07 | 1987-04-15 | Hitachi Micro Comput Eng Ltd | リ−ドフレ−ムおよびそれを用いた半導体装置 |
CN104641466A (zh) * | 2012-11-19 | 2015-05-20 | 富士电机株式会社 | 半导体装置 |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6411095U (ja) * | 1987-07-10 | 1989-01-20 |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS50674U (ja) * | 1973-05-01 | 1975-01-07 | ||
JPS5278372A (en) * | 1975-12-25 | 1977-07-01 | Nec Corp | Method of blanking of lead frame for electronic parts |
JPS53119862U (ja) * | 1977-02-28 | 1978-09-22 | ||
JPS5494157U (ja) * | 1977-12-16 | 1979-07-03 |
-
1979
- 1979-11-22 JP JP15065479A patent/JPS5674948A/ja active Granted
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS50674U (ja) * | 1973-05-01 | 1975-01-07 | ||
JPS5278372A (en) * | 1975-12-25 | 1977-07-01 | Nec Corp | Method of blanking of lead frame for electronic parts |
JPS53119862U (ja) * | 1977-02-28 | 1978-09-22 | ||
JPS5494157U (ja) * | 1977-12-16 | 1979-07-03 |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6281738A (ja) * | 1985-10-07 | 1987-04-15 | Hitachi Micro Comput Eng Ltd | リ−ドフレ−ムおよびそれを用いた半導体装置 |
JPH0455341B2 (ja) * | 1985-10-07 | 1992-09-03 | Hitachi Maikuro Konpyuuta Enjiniaringu Kk | |
CN104641466A (zh) * | 2012-11-19 | 2015-05-20 | 富士电机株式会社 | 半导体装置 |
US9728475B2 (en) | 2012-11-19 | 2017-08-08 | Fuji Electric Co., Ltd. | Lead portion of semiconductor device |
Also Published As
Publication number | Publication date |
---|---|
JPS6230498B2 (ja) | 1987-07-02 |
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