JPS5674929A - Insulating layer forming method - Google Patents

Insulating layer forming method

Info

Publication number
JPS5674929A
JPS5674929A JP15185279A JP15185279A JPS5674929A JP S5674929 A JPS5674929 A JP S5674929A JP 15185279 A JP15185279 A JP 15185279A JP 15185279 A JP15185279 A JP 15185279A JP S5674929 A JPS5674929 A JP S5674929A
Authority
JP
Japan
Prior art keywords
concentration
injected
ion
layer
distribution
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP15185279A
Other languages
Japanese (ja)
Other versions
JPS6212658B2 (en
Inventor
Takayoshi Hayashi
Hamao Okamoto
Yoshikazu Honma
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Telegraph and Telephone Corp
Original Assignee
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Telegraph and Telephone Corp filed Critical Nippon Telegraph and Telephone Corp
Priority to JP15185279A priority Critical patent/JPS5674929A/en
Publication of JPS5674929A publication Critical patent/JPS5674929A/en
Publication of JPS6212658B2 publication Critical patent/JPS6212658B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Formation Of Insulating Films (AREA)

Abstract

PURPOSE:To eliminate a boundary layer including a fault and polycrystal by a method wherein a substrate is controlled to conform with a temperature in which a heat diffusion and a chemical reaction are produced and ion of a concentration required for forming an equalized SiO2 or more is injected. CONSTITUTION:When ion is injected into a Si substrate which is retained in 200 deg.C or more, finally, a vicinity of a depth 6 reaches a sufficient concentration to form an equlized SiO2 layer. When ion is injected more, an excessive O2 is diffused by heat to react with a nonreaction Si. When an injection quantity is increased, a distribution of the O2 concentration to the depth direction varies (from 7 to 10). The sharp change of distribution becomes remarkable from an injection quantity 8 which is 1.5 times of the existing method (4.5X10<22>/cm<3>). When the concentration becomes 2 times, an extremely sharp distribution 10 is indicated. As a result thereof, no boundary layer exists utterly between a superficial mono crystal layer 11 and an internal compound layer 12 and the crystalline becomes outstandingly good, and if an IC is formed thereupon, its characteristic is good. And further, the thickness of an insulating layer can be accurately controlled by an injection energy and an injection quantity.
JP15185279A 1979-11-22 1979-11-22 Insulating layer forming method Granted JPS5674929A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15185279A JPS5674929A (en) 1979-11-22 1979-11-22 Insulating layer forming method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15185279A JPS5674929A (en) 1979-11-22 1979-11-22 Insulating layer forming method

Publications (2)

Publication Number Publication Date
JPS5674929A true JPS5674929A (en) 1981-06-20
JPS6212658B2 JPS6212658B2 (en) 1987-03-19

Family

ID=15527668

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15185279A Granted JPS5674929A (en) 1979-11-22 1979-11-22 Insulating layer forming method

Country Status (1)

Country Link
JP (1) JPS5674929A (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3139904B2 (en) * 1993-12-28 2001-03-05 新日本製鐵株式会社 Method and apparatus for manufacturing semiconductor substrate
KR102484068B1 (en) 2021-10-22 2023-01-04 (주)코리아테크 Stick type container
KR102482185B1 (en) 2022-09-15 2022-12-29 (주)코리아테크 Stick type container

Also Published As

Publication number Publication date
JPS6212658B2 (en) 1987-03-19

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