JPS5673453A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS5673453A
JPS5673453A JP15125679A JP15125679A JPS5673453A JP S5673453 A JPS5673453 A JP S5673453A JP 15125679 A JP15125679 A JP 15125679A JP 15125679 A JP15125679 A JP 15125679A JP S5673453 A JPS5673453 A JP S5673453A
Authority
JP
Japan
Prior art keywords
wiring
silicide
alsi
contact resistance
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP15125679A
Other languages
Japanese (ja)
Inventor
Masahiro Yamada
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Suwa Seikosha KK
Original Assignee
Seiko Epson Corp
Suwa Seikosha KK
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp, Suwa Seikosha KK filed Critical Seiko Epson Corp
Priority to JP15125679A priority Critical patent/JPS5673453A/en
Publication of JPS5673453A publication Critical patent/JPS5673453A/en
Pending legal-status Critical Current

Links

Landscapes

  • Electrodes Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PURPOSE:To reduce sharply the contact resistance of a wiring against the upper layer wiring in a semiconductor device by a method wherein against the wiring of Ta or Ta silicide oxidizable easily, a metal or the metal silicide having a different melting point is arranged to form the two layer structure. CONSTITUTION:A polycrystalline Si gate electrode 204 is formed against a gate oxide film 203 and an N<+> layer 202 on a P type substrate 201, and the Ta wiring 205, an Mo silicide 206 are laminated consecutively. Then it is covered with a CVD SiO2 film 207, and after it is heat treated in N2 gas, the wiring 208 is formed with AlSi. When the Ta 205 and the Mo silicide 206 are evaporated consecutively in this way, the generation of a Ta oxide on the Ta can be prevented considerably, and because the stable Mo silicide 206 exists on the Ta, so that the contact resistance with the AlSi 208 is reduced.
JP15125679A 1979-11-20 1979-11-20 Semiconductor device Pending JPS5673453A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15125679A JPS5673453A (en) 1979-11-20 1979-11-20 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15125679A JPS5673453A (en) 1979-11-20 1979-11-20 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS5673453A true JPS5673453A (en) 1981-06-18

Family

ID=15514680

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15125679A Pending JPS5673453A (en) 1979-11-20 1979-11-20 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS5673453A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6577005B1 (en) * 1997-11-27 2003-06-10 Kabushiki Kaishia Toshiba Fine protuberance structure and method of production thereof

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6577005B1 (en) * 1997-11-27 2003-06-10 Kabushiki Kaishia Toshiba Fine protuberance structure and method of production thereof

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