JPS5666064A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS5666064A JPS5666064A JP14178479A JP14178479A JPS5666064A JP S5666064 A JPS5666064 A JP S5666064A JP 14178479 A JP14178479 A JP 14178479A JP 14178479 A JP14178479 A JP 14178479A JP S5666064 A JPS5666064 A JP S5666064A
- Authority
- JP
- Japan
- Prior art keywords
- junction
- capacitance
- film
- substrate
- region
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
Landscapes
- Semiconductor Integrated Circuits (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Semiconductor Memories (AREA)
Abstract
PURPOSE:To make the junction capacitance large when a junction face is to be formed in a semiconductor device by a method wherein the face thereof is constituted of shallow parts and deep parts to enlarge the junction area per unit area. CONSTITUTION:When the MOS dynamic RAM is to be formed, a thick separating oxide film 3 is formed at the circumference of a P type Si substrate 1, and an N<+> type region 2 to form a bit line is formed by diffusion in the substrate 1 being surrounded with the film. The junction capacitance consisting of a P<+> type region 4 and an adjacent N<+> type region 5 is formed in the substrate 1 locating between the film 3 and the region being close to the film 3, and the second polycrystalline Si layer 7 is formed on it with the intermediary of the second oxide film 6 being located between them. Then the second polycrystalline Si layer 9 is adhered thereon between the film 3 and the region 2 via the first oxide film 8 between them to use it as gate capacitance. In this consitution, the junction capacitance is consisted of shallow junction faces 10a and deep junction faces 10b forming an uneven face to enlarge the junction area, and the large cell capacitance consisting of the sum of the junction capacitance and the gate capacitance is obtained.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP14178479A JPS5666064A (en) | 1979-10-31 | 1979-10-31 | Semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP14178479A JPS5666064A (en) | 1979-10-31 | 1979-10-31 | Semiconductor device |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS5666064A true JPS5666064A (en) | 1981-06-04 |
JPS6243347B2 JPS6243347B2 (en) | 1987-09-12 |
Family
ID=15300076
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP14178479A Granted JPS5666064A (en) | 1979-10-31 | 1979-10-31 | Semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5666064A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6037765A (en) * | 1983-08-11 | 1985-02-27 | Nec Corp | Semiconductor device and manufacture thereof |
-
1979
- 1979-10-31 JP JP14178479A patent/JPS5666064A/en active Granted
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6037765A (en) * | 1983-08-11 | 1985-02-27 | Nec Corp | Semiconductor device and manufacture thereof |
JPH0367348B2 (en) * | 1983-08-11 | 1991-10-22 | Nippon Electric Co |
Also Published As
Publication number | Publication date |
---|---|
JPS6243347B2 (en) | 1987-09-12 |
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