JPS5666046A - Processing method of semiconductor substrate - Google Patents

Processing method of semiconductor substrate

Info

Publication number
JPS5666046A
JPS5666046A JP14190779A JP14190779A JPS5666046A JP S5666046 A JPS5666046 A JP S5666046A JP 14190779 A JP14190779 A JP 14190779A JP 14190779 A JP14190779 A JP 14190779A JP S5666046 A JPS5666046 A JP S5666046A
Authority
JP
Japan
Prior art keywords
wafer
impairing
main surface
gettering
region
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP14190779A
Other languages
Japanese (ja)
Inventor
Akira Kojima
Masaki Okayama
Norihiro Kusumoto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sony Corp
Original Assignee
Sony Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Corp filed Critical Sony Corp
Priority to JP14190779A priority Critical patent/JPS5666046A/en
Publication of JPS5666046A publication Critical patent/JPS5666046A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Bipolar Transistors (AREA)

Abstract

PURPOSE:To attain satisfactory effects simply with high productivity by a method wherein gettering is conducted in such a state that impairment is inflicted on part of the main surface of a semiconductor by injecting Kr ions. CONSTITUTION:Kr<+> are injected into part of the main surface of an Si wafer at an acceleration voltage of 35-300kV with a dosing quantity equal to 10<13>-10<6>/cm<2> while a suitable peak range is selected. Then, it is heat-oxidized, annealed and so processed that an Al electrode is formed. As a result, the crystallization of the wafer and the carrier life are improved and lengthened. Since Kr<+> according to this method is inert, the furnace is unpolluted, making unnecessary the coating of the back. The gettering region with the desired impairing density in the wafer can be readily formed, while the sufficient impairing region can be formed with a small dosing quantity since Kr has large mass.
JP14190779A 1979-11-01 1979-11-01 Processing method of semiconductor substrate Pending JPS5666046A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14190779A JPS5666046A (en) 1979-11-01 1979-11-01 Processing method of semiconductor substrate

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14190779A JPS5666046A (en) 1979-11-01 1979-11-01 Processing method of semiconductor substrate

Publications (1)

Publication Number Publication Date
JPS5666046A true JPS5666046A (en) 1981-06-04

Family

ID=15302927

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14190779A Pending JPS5666046A (en) 1979-11-01 1979-11-01 Processing method of semiconductor substrate

Country Status (1)

Country Link
JP (1) JPS5666046A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60117738A (en) * 1983-11-30 1985-06-25 Sanken Electric Co Ltd Manufacture of semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60117738A (en) * 1983-11-30 1985-06-25 Sanken Electric Co Ltd Manufacture of semiconductor device

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