JPS60117738A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To improve the breakdown voltage characteristic of p-n junction by a gettering effect by forming an ion implantation layer which is ions implanted more than the threshold implantation quantity followed by heat treatment of 300-600 deg.C after completing the all heat treatment over 600 deg.C. CONSTITUTION:An n<+> type emitter layer 4 and an n<+> type diffusion layer 5 for a ohmic contact of a collector electrode are formed and a process of heat treatment over 600 deg.C is completed in this process. Subsequently, for the whole of back surface of a wafer 1, Ar implantation over a threshold implantation quantity of Ar is performed to form an ion implantation layer 6 which is made to be amorphous. Next, holes are opened on an SiO2 film and Al is patterned followed by heat treatment with 480 deg.C in an N2 atmosphere to form an emitter electrode 7, a base electrode 8 and a collector electrode 9. The heat treatment at forming these electrodes also works concurrently as the heat treatment for causing a gettering effect in the ion implantation layer 6.

Description

DETAILED DESCRIPTION OF THE INVENTION TECHNICAL FIELD The present invention relates to a method for improving breakdown voltage characteristics of a semiconductor device by gettering.

"Prior Art" If polymerization end ions or the like exist in the vicinity of a Pn junction, the electric field concentrates in that part, leading to local breakdown before the breakdown of the entire junction, resulting in a reduction in breakdown voltage. For this reason, mechanical strain is applied by sandblasting or ion implantation to parts that do not adversely affect the operation of semiconductor devices, such as the backside of semiconductor wafers, and heavy metal ions, etc. are fixed in this strained layer to improve withstand voltage characteristics. A so-called gettering technique is known.

An example of gettering by ion implantation will be explained in the case of a silicon transistor. First, a P-type base layer is formed by diffusing boro/on the surface of a silicon wafer.

Next, after implanting Ar (argon) ions into the back surface of the phenol, phosphorus is diffused onto the surface of the phenol to form a male-shaped emitter layer and a shape expanding layer for the ohmic contact of the collector electrode. By implanting Ar, the vicinity of the back surface of the phenol becomes amorphous and many crystal defects are generated. These crystal defects are propagated to the surface side of the oxide film by the subsequent heat treatment for phosphorus diffusion, and exert a gettering effect that fixes heavy metal ions and the like.

In this way, gettering by conventional ion implantation is
It was believed that it was necessary to perform heat treatment after ion implantation at a relatively high temperature, so this heat treatment was
This was done by taking advantage of the heat treatment at about 0 to 1200°C.

On the other hand, the inventors of the present application have experienced the above conventional gettering and found that when Ar ions were implanted into the back surface of the silicon urchin and heat treated at approximately 1100°C, crystal defects caused by the ion implantation were removed from the wafer. It has been found that new crystal defects that cause a decrease in breakdown voltage may be formed due to distortion caused by diffusion and interaction with dirt that has entered from the surface. For this reason, it has been speculated that conventional gettering has the effect of improving breakdown voltage as well as the effect of canceling that effect.

[Object of the Invention] An object of the present invention is to improve the gettering effect by ion implantation and to improve the breakdown voltage characteristics of a semiconductor device.

Embodiment FIG. 1 shows a method of manufacturing a silicon transistor to which the present invention is applied.

tf, 8i (
Perform selective diffusion of boron using the h film (2) as a mask,
A P-type base layer (3) with a depth of 2μ was formed (first round included)
reference). The diffusion temperature is 950° C. for pre-deposition using BBrs as an impurity source, and 1150° C. for drive-in.

Next, the base layer surface and the wafer (1
) to perform selective diffusion of phosphorus on the surface of the n+
A J-shaped emitter layer (4) and a J-shaped compensation layer (5) for ohmic contact of the collector electrode were formed (Fig. 1(B)).
reference). The diffusion temperature is 950° C. for pre-deposition using POCls as an impurity source, and 1000° C. for drive-in. At this time, the base width was 1 μm due to the emitter extrusion effect. It should be noted that more than 6,000 heat treatment steps were completed in this step.

Subsequently, I
Argon implantation was performed at 1 o" (l!/cd), and the wafer (
1) An amorphous ion-implanted layer (6
) was formed (see Figure 1(C)).

Next, holes were opened in the SiO2 film (2), At was deposited by electron beam, and the bale with patterned At was heat-treated at 480°C for 30 minutes in a N2 atmosphere, and the emitter electrode (7
), a base electrode (8) and a collector electrode (9) were formed (see FIG. 1(D)). This heat treatment during electrode formation also serves as a heat treatment for causing the ion-implanted layer (6) to exhibit a gettering effect.

In this example, in order to clarify the effect of gettering, the bead area is 1μ for the base width 1μ.
A transistor with a large area of 8.36 fJ and an emitter area of 1766 mm was formed. For this reason, the non-defective product rate is quite low. The wafer thickness was 280μ.

"Effects of the Invention" Figure 2 shows data comparing the collector-base junction breakdown voltage BVCBO of the transistor according to the present invention shown in Figure 1 (D) and the conventional transistor. The conventional transistor is a transistor that is produced immediately before the emitter diffusion in the Ar injection step in the manufacturing process shown in FIG. 1, and other than that, it is manufactured in exactly the same process as the transistor according to the present invention.

According to the withstand voltage histogram in FIG. 2, the transistor according to the present invention has a BVCBO
is found to be high overall. Also, BVCBO is 10
The number of samples of 0 V or more was 21 out of 63 (33.3%) for the conventional transistor, while it was 27 out of 63 (429%) for the transistor according to the present invention.
An improvement in pressure resistance yield was observed. Furthermore, the current −■,
When observed using a voltage characteristic curve tracer 2, the number of samples exhibiting sharp breakdown characteristics (A-de breakdown) was greater in the transistor according to the present invention than in the case of conventional transistors.

The reason for this improvement in breakdown voltage characteristics is that the temperature of the heat treatment performed after ion implantation is significantly lower than that of conventional methods7.
This is thought to be because the propagation of the crystal defects caused by ion implantation to the wafer surface side is small, and no new crystal defects are generated due to the interaction described in the conventional example section.

Further, it is believed that this is because by setting the ion implantation amount to the critical implantation level of 41 or more, the gettering effect is sufficiently exhibited even when heat treatment is performed on a relatively small groove.

In the present invention, since the heat treatment temperature is low, there is a possibility that the amorphous ion-implanted layer may not be sufficiently recrystallized. However, it is believed that the region that becomes amorphous does not have much effect on the operation of the semiconductor device, and that although it has a lower temperature history than conventionally, some recrystallization will occur. No problems occur.

``Others'' Elements to be implanted for gettering ions,
Argon, oxygen and phosphorous are effective for silicon wafers. However, it is not impossible to use other elements as well. - As mentioned above, the ion implantation amount should be greater than the critical implantation level to ensure gettering effectiveness. As shown in Figure 3, the critical implantation dose is the implantation dose at which the crystal defect density that generates the ion-implanted layer is saturated by ion implantation, and corresponds to the implantation dose at which the ion-implanted area becomes completely amorphous. do. The reason why the crystal defect density slightly decreases when the critical implantation dose is exceeded is considered to be that recrystallization of the amorphous layer becomes more dominant than the generation of crystal defects due to ion implantation.

The heat treatment temperature after ion implantation is practically 300°C.
~600°C is suitable. That is, when the temperature exceeds 600° C., the negative effect that crystal defects have on the breakdown voltage characteristics increases. If the temperature is less than 300° C., sufficient movement of 0L metal ions and the like does not occur, so the gettering effect is small. The heat treatment time is not a factor in reducing heat treatment, but if it is too short, gettering will not occur sufficiently, so the heat treatment time should be at least 15 minutes or more, usually about 30 minutes or more.

As for the region to be ion-implanted, if the semiconductor device is built substantially near the surface of the semiconductor unit I, as in the example, the ion implantation for gettering is performed in the region on the back side of the semiconductor unit I. It is better.

2.-1-.Furthermore, even in the case of the embodiment, the region surrounding the Pn junction (particularly the vicinity of the cutting region for chipping) can be selected as the ion implantation region. Furthermore, ions can be implanted shallowly into the surface of the emitter region within a range that does not adversely affect the emitter junction. Of course, this does not mean that ions must be implanted over the entire surface of these regions, but ions may be implanted only in the region facing the Pn junction on the back surface of the wafer, or in the vertical and horizontal cut regions on the front surface of the wafer. It is also possible to adopt a method in which ions are implanted only along the longitudinal cut region. Further, in the case of an epitaxial two-rj-four diffusion type transistor or a three-wheel extended type transistor, an emitter layer and a space layer are formed on the wafer surface side, and a thick collector high resistance layer is formed on the wafer surface side. However, this collector high resistance layer has little to do with transistor operation.

FIG. 2 is a sectional view showing a method of manufacturing a resistor.
FIG. 3 is a histogram of the BVCBO of the embodiment and the conventional example, and is a graph illustrating the critical implantation dose in ion implantation.

(1)...N-type silicon unino, (3)...P-type paste layer.

(4)...C-type emitter layer, (6)...ion implantation layer.

(7)...Emitter electrode.

Patent applicant: Sanken Electric Co., Ltd. Engraving of drawings (no changes in content) Figure 1 Figure 2' BVc8. (V) Figure 3/-' - Io + Injection amount Io〉Yo Main X amount procedural amendment (voluntary) December 7, 1982 1, Indication of matter ';';j' 2Z 2771 1977
Patent application 2 filed on November 30, 1988. Title of invention: Method for manufacturing a semiconductor device 3. Person making the amendment 4. Full text of the specification to be amended and drawings.

5. Description of the amendment 1t + engraving of the book (no change in content) and engraving of drawings (no change in content).

Claims (2)

[Claims] (1) 600°C for a semiconductor substrate on which at least one Pn junction or Schottky junction is formed.
After completing all heat treatments exceeding 300 mL, an ion implantation layer with ions implanted at a critical dose or higher is formed in a region that does not substantially adversely affect the operation of the semiconductor device to be finally formed. A method for manufacturing a semiconductor device I-P, characterized in that heat treatment is performed at ~600° C. to improve breakdown voltage characteristics of the P% junction by gettering action based on the ion-implanted layer. (2) The method of manufacturing a semiconductor device according to claim 1, wherein the heat treatment at 600° C. or less is performed also as heat treatment of the electrode metal.