JP2008004704A - Method of manufacturing semiconductor element - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To solve the problem that, if a heavy metal is diffused in a semiconductor wafer 10, an effect of shortening the life time of minority carriers can be obtained, however, an adverse effect associated with the diffusion of the heavy metal also occurs. <P>SOLUTION: Before diffusing the heavy metal 7 into the semiconductor wafer 10, an inactive element Ar is injected into the semiconductor wafer 10. At that time, Ar is injected from the surface 2a of the semiconductor wafer 10 above a position where a pn junction is formed in the semiconductor wafer 10. Thereafter, the heavy metal 7 is diffused. By the ion implantation of Ar, an amorphous structure 6 is formed in the semiconductor wafer 10, the heavy metal is evenly diffused by the amorphous structure 6, and hence the adverse effect due to the diffusion of the heavy metal can be eliminated. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a method for manufacturing a semiconductor element, and more particularly to a method for manufacturing a semiconductor element in which heavy metals are added as a lifetime killer for minority carriers.

  In a semiconductor element having a PN junction, in order to improve the switching speed of the element, it is known that heavy metals such as Au (gold) and Pt (platinum) are diffused into the semiconductor substrate as a minority carrier lifetime killer. . Heavy metal diffused in the semiconductor substrate constitutes a trap for minority carriers. Minority carriers are recombined through this trap, the minority carrier lifetime is shortened, and the switching speed is improved. As a result, a semiconductor element having a high operating frequency can be obtained.

A method for manufacturing a semiconductor element to which a heavy metal is added is disclosed in Patent Document 1, for example. A semiconductor device manufacturing method (conventional semiconductor device manufacturing method) disclosed in Patent Document 1 will be described with reference to the drawings.
FIG. 6 is a diagram for explaining a conventional method of manufacturing a semiconductor element. As shown in FIG. 6A, first, an N type epitaxial layer 22 is formed on an N + type semiconductor substrate 21. The N + type semiconductor substrate 21 and the N type epitaxial layer 22 constitute a semiconductor wafer 30. An oxide film 23 is formed on the surface of the N-type epitaxial layer 22, and an opening 24 is formed in a part of the oxide film 23. A P-type diffusion layer 25 is formed in the N-type epitaxial layer 22 exposed through the opening 24. Subsequently, the heavy metal 26, for example, Pt (platinum), Au (gold), or the like is sputtered to attach the heavy metal 26 to the surface of the P-type diffusion layer 25.

Thereafter, as shown in FIG. 6B, the semiconductor wafer 30 is heat-treated to diffuse the heavy metal 26 into the semiconductor wafer 30.
JP-A-6-342799

  In the conventional method for manufacturing a semiconductor element described above, diffusing heavy metal in the semiconductor wafer 30 has the effect of shortening the minority carrier lifetime and improving the switching speed, while being inherent in the semiconductor wafer 30. The effects of distortion, defects, etc. (indicated by reference numeral 27) appear as side effects. This side effect has the problem that the reverse direction characteristics of the semiconductor element after heavy metal diffusion may become unstable and the leakage current may increase.

Accordingly, a main object of the present invention is to provide a method of manufacturing a semiconductor element capable of preventing heavy metal from being unevenly diffused due to the influence of strain, defects, etc. inherent in a semiconductor wafer when adding heavy metal. .
Another object of the present invention is to provide a method of manufacturing a semiconductor device suitable for high-speed switching by diffusing heavy metals well as a minority carrier lifetime killer.

  The invention according to claim 1 is a method of manufacturing a semiconductor device in which heavy metal is added as a minority carrier lifetime killer, the step of preparing a semiconductor wafer on which a PN junction is formed, and a position where the PN junction is formed A step of injecting an inert element from the surface of the upper semiconductor wafer, a step of attaching heavy metal to the surface of the semiconductor wafer on the position where the PN junction is formed, and a step of applying heat treatment to the semiconductor wafer to attach the heavy metal And a step of diffusing the semiconductor element into the semiconductor wafer.

The invention according to claim 2 is characterized in that the step of injecting the inert element into the semiconductor wafer includes the step of amorphizing the position of the integrated depth from the surface of the semiconductor substrate. It is a manufacturing method of a semiconductor element.
A third aspect of the present invention is the method of manufacturing a semiconductor element according to the first or second aspect, wherein the inert element contains Ar (argon).

The invention according to claim 4 includes the step of implanting Ar (argon) at a dose of 1 × 10 ¹⁴ to 1 × 10 ¹⁶ / cm ² and an acceleration voltage of 20 to 160 KeV. The method of manufacturing a semiconductor device according to claim 3, wherein the method is characterized in that:
The invention according to claim 5 is the method for manufacturing a semiconductor element according to any one of claims 1 to 4, wherein the semiconductor element includes a fast recovery diode.

According to the first aspect of the present invention, before the heavy metal is diffused into the semiconductor wafer, the inert element is first implanted into the semiconductor wafer. The inert element is implanted from the surface of the semiconductor wafer on the position where the PN junction is formed in the semiconductor wafer.
When heavy metal is deposited on the surface of the semiconductor wafer after the inert element is implanted, and the deposited heavy metal is diffused into the semiconductor wafer by heat treatment, the heavy metal is diffused evenly in the semiconductor wafer. This is because the strain and defects in the semiconductor wafer are made uniform by the implanted inert element.

The step of injecting the inert element into the semiconductor wafer is performed by amorphizing the crystallized semiconductor layer at a certain depth from the surface of the semiconductor wafer to form the amorphous material at a certain depth. It is preferable to include the process of changing to a state.
The amorphous layer formed in the semiconductor wafer makes the strain and defects in the semiconductor wafer uniform, and cancels the problem that heavy metal diffusion is partially affected by the strain and defects scattered in the semiconductor wafer. Work.

If the inert element is Ar (argon) as described in claim 3, the inert element can be easily implanted, and an amorphous region can be formed at a predetermined depth of the semiconductor wafer. it can.
Further, when the inert element is Ar (argon), it is desirable to inject with the dose amount and the acceleration voltage according to claim 4. By injecting with the dose amount and the acceleration voltage, the semiconductor element is formed as the semiconductor element. The described fast recovery diode can be suitably manufactured.

Hereinafter, a method for manufacturing a fast recovery diode will be specifically described as a method for manufacturing a semiconductor device according to an embodiment of the present invention with reference to the drawings.
1A to 1F are illustrative views showing step by step a process for manufacturing a fast recovery diode by a manufacturing method according to an embodiment of the present invention.
First, as shown in FIG. 1A, an N + type semiconductor substrate 1 is prepared. The semiconductor substrate 1 has two flat main surfaces (an upper surface and a lower surface) facing each other. N epitaxial layer 2 is formed on one main surface (for example, the upper surface) of semiconductor substrate 1. The N + type semiconductor substrate 1 and the N epitaxial layer 2 constitute a semiconductor wafer 10.

Next, referring to FIG. 1A, an insulating film 3 made of a silicon oxide film or the like is formed on the upper surface (main surface) 2 a of the N epitaxial layer 2. Then, an opening 4 is formed in the insulating film 3. The opening 4 is formed in a portion corresponding to a region where the P-type semiconductor region is to be formed. The insulating film 3 in which the opening 4 is formed functions as a mask in a process described later.
Next, a P-type impurity (for example, boron) is selectively diffused into the N epitaxial layer 2 through the opening 4 of the insulating film 3 to form a P-type semiconductor region 5. For the selective diffusion of the P-type impurity, a conventionally known thermal diffusion method or ion implantation method can be used, whereby the P-type semiconductor region 5 can be formed. By forming the P-type semiconductor region 5, a PN junction is formed between the N epitaxial layer 2 and the P-type semiconductor region 5.

Next, as shown in FIG. 1B, with the insulating film 3 as a mask, an inert element such as Ar (argon), for example, 1 × 10 ¹⁴ to 1 × 10 ¹⁶ / cm ^{2 is} formed from the opening 4 of the insulating film 3. The ion implantation is performed with an acceleration voltage of 20 to 160 KeV. The region into which Ar is implanted is a PN junction region, which is a contact region when the anode electrode is formed.
As shown in FIG. 1C, when Ar is ion-implanted, the implanted Ar partially changes the crystal structure of the P-type semiconductor region 5. More specifically, when Ar is ion-implanted, the crystal structure of the P-type semiconductor region 5 at a certain depth from the surface 2a of the semiconductor wafer 10 changes. That is, the P-type semiconductor region 5 having a single crystal structure is changed to an amorphous structure 6 at a constant depth. When the amorphous structure 6 is formed on the semiconductor wafer 10, the portion where the amorphous structure 6 is formed becomes uniform within a certain strain range.

On the other hand, when Ar ion implantation is not performed, nonuniform strains are scattered in the region of the semiconductor wafer 10 where the PN junction is formed. In the conventional manufacturing method, this non-uniform distortion has been one of the causes that prevent the heavy metal from diffusing uniformly when diffusing the heavy metal as a minority carrier lifetime killer.
On the other hand, according to the manufacturing method of the present invention, the amorphous structure 6 formed by ion implantation of an inert element makes the distortion uniform within a certain range, and the diffusion of heavy metal as a lifetime killer is performed uniformly. Acts as follows.

  Next, as shown in FIG. 1D, for example, Pt (platinum) 7 is deposited as a heavy metal on the surface of the semiconductor wafer 10 through the opening 4 of the insulating film 3 using the insulating film 3 as a mask. The adhesion of Pt7 can be realized using a sputtering technique. Also, Pt7 can be attached using a vacuum deposition method. The adhesion amount and film thickness of Pt7 are determined according to the characteristics of the semiconductor element to be manufactured.

  Next, as shown in FIG. 1E, the semiconductor wafer 10 to which Pt7 is attached is subjected to heat treatment. The heating time and heating temperature are roughly determined by the amount of heavy metal deposited (in this case Pt7). For example, in the case of Pt, it is desirable that the heat treatment is performed at about 1100 ° C. for about 60 minutes. When heat treatment is performed on the semiconductor wafer 10, Pt 7 attached to the surface of the semiconductor wafer 10 is diffused through the amorphous structure 6 into the semiconductor wafer 10. The amorphous structure 6 is uniform within a certain strain range. That is, the amorphous structure 6 has a uniform strain. Therefore, Pt 7 on the surface of the semiconductor wafer 10 is uniformly diffused into the P-type semiconductor region 5 and the N epitaxial layer 2 through an amorphous structure formed at a certain depth from the surface.

Further, when the semiconductor wafer 10 is heat-treated, the amorphous structure 6 is recrystallized along with the diffusion of heavy metal, so that the amorphous structure 6 that has been amorphousized by the implantation of the inert element disappears, and the function as a semiconductor element is defective. Will not affect.
Thereafter, as shown in FIG. 1F, the P-type semiconductor region 5 is exposed on the surface of the semiconductor wafer 10, and an anode electrode 8 as a first electrode that is electrically joined to the P-type semiconductor region 5 is formed. The The metal forming the anode electrode 8 can be appropriately selected. Further, a cathode electrode 9 as a second electrode to be electrically joined is formed on the back surface of the semiconductor wafer 10. The metal forming the cathode electrode 9 can also be selected as appropriate. Formation of the anode electrode 8 and the cathode electrode 9 can be realized by using a conventionally known technique such as a vapor deposition method, a sputtering method, or a CVD method.

Next, characteristics and the like of the semiconductor element manufactured by the manufacturing method according to one embodiment of the present invention will be described with reference to FIGS.
FIG. 2 is a graph showing the yield at the time of manufacturing a semiconductor device manufactured by the manufacturing method according to one embodiment of the present invention. In the graph of FIG. 2, a semiconductor element in which Ar was not implanted as an inert element (Comparative Example 1), and a semiconductor element in which Ar was implanted at a dose of 1 × 10 ¹⁵ / cm ² (Comparative Example 2). ) And the yield of each of the semiconductor elements (Examples) in which Ar ion implantation was performed at a dose of 3 × 10 ¹⁵ / cm ² . Note that Ar ion implantation was performed at an acceleration voltage of 30 KeV.

  As can be seen from FIG. 2, the yield of the semiconductor element during manufacturing was improved by implanting Ar as an inert element. That is, in the conventional method for manufacturing a semiconductor device (Comparative Example 1), the yield was 75%, but by implanting ions with a relatively small dose (Comparative Example 2), the yield of the semiconductor device was increased to 80%. %. Furthermore, it was confirmed that the yield of the semiconductor element can be improved to 95% by relatively increasing the dose amount to be within the range of the present invention.

  FIG. 3 shows a semiconductor device manufactured according to one embodiment of the present invention (Example D), a semiconductor device manufactured by changing the location of ion implantation of an inert element (Comparative Examples B and C), and an inert element. It is a graph showing the difference of a yield with the semiconductor element (comparative example A) which did not perform ion implantation of this. As is apparent from FIG. 3, the yield of the semiconductor device (Comparative Example A) in which Ar ions were not implanted, the yield of the semiconductor device in which Ar was ion implanted from the back surface of the semiconductor wafer 10 (Comparative Example B), and Ar as PN The yield of the semiconductor element (Comparative Example C) implanted with ions other than the contact region of the junction region is approximately 75%. In contrast, in the semiconductor device manufactured according to the embodiment of the present invention (Example D), Ar is ion-implanted into the contact region of the PN junction region as an inert element, but the yield is about 95%. The yield was improved.

FIG. 4 shows a semiconductor element in which Ar as an inert element is ion-implanted into the contact region on the PN junction region of the semiconductor wafer 10, and the characteristics of the reverse voltage when the acceleration voltage is changed are compared. It is a graph.
Specifically, Ar doses were fixed at 3 × 10 ¹⁵ / cm ² and acceleration voltages were changed to 30 KeV, 50 KeV, and 100 KeV, and their characteristics were compared.

As a result of comparison, when the acceleration voltage was 30 KeV, the reverse voltage (BV) showed the largest value at about 380 (V). Next, a value of about 370 (V) was shown at 50 KeV, and a value of about 360 (V) was shown at 100 KeV.
Even when the acceleration voltage was 100 KeV or higher, it was confirmed that when the reverse voltage required for the fast recovery diode is low, the reverse voltage is within a sufficiently usable range.

  Finally, FIG. 5 shows a semiconductor element in which an inert element is not ion-implanted (Comparative Example: FIG. 5A) and a semiconductor element manufactured by the manufacturing method according to one embodiment of the present invention (Example: FIG. B)), the reverse current (IR) and reverse voltage (BV) characteristics were measured. As is apparent from FIG. 5, it can be seen that the semiconductor device (Example) manufactured by the manufacturing method according to the embodiment of the present invention has a stable characteristic waveform in the reverse direction.

As will be apparent from the description of the embodiment described above, the semiconductor wafer 10, more specifically, the adverse effect of strains and defects inherent in the silicon upon diffusion of heavy metal, can be reduced with an inert element such as Ar. Mitigated by ion implantation.
As a result, the reverse characteristic waveform of the manufactured semiconductor element can be improved.
In addition, with the improvement of the reverse characteristic waveform, the yield of the manufactured semiconductor element is also improved.

Furthermore, the characteristics of the semiconductor element to be manufactured can be adjusted according to the acceleration voltage and conditions at the time of implantation of the inert element to be ion-implanted. That is, the processing position in the depth direction of the inert element to be ion-implanted can be changed by changing the acceleration voltage, and the characteristics can be changed. Therefore, it is possible to match the desired characteristics.
The present invention is not only effective for the embodiment described above, that is, the method for manufacturing the fast recovery diode, but can be applied to all the manufacturing methods for changing the characteristics of the semiconductor element by diffusing heavy metal into the semiconductor wafer. .

  In addition, the present invention is not limited to the above description, and various modifications can be made within the scope of the claims.

It is the illustration figure which showed the process of manufacturing a fast recovery diode by the manufacturing method which concerns on one Embodiment of this invention in steps. It is a graph showing the yield at the time of manufacture of the semiconductor element manufactured by the manufacturing method concerning one embodiment of this invention. It is a graph showing the difference of the yield of the semiconductor element manufactured by one Embodiment of this invention, and a comparative example. 5 is a graph comparing the characteristics of the reverse voltage when the acceleration voltage is changed in Ar ion implantation. It is the graph which compared the characteristic of the reverse current of the semiconductor element which does not ion-implant an inert element, and the implanted semiconductor element. It is a figure for demonstrating the manufacturing method of the conventional semiconductor element.

Explanation of symbols

1 N + type semiconductor substrate 2 N epitaxial layer 3 insulating film 4 opening 5 P type semiconductor region 6 amorphous structure 7 Pt (platinum)
8 Anode electrode 9 Cathode electrode 10 Semiconductor wafer

Claims (5)

A method for manufacturing a semiconductor element in which heavy metals are added as a lifetime killer of minority carriers,
Preparing a semiconductor wafer on which a PN junction is formed;
Injecting an inert element from the surface of the semiconductor wafer on the position where the PN junction is formed;
Attaching heavy metal to the surface of the semiconductor wafer on the position where the PN junction is formed;
Performing a heat treatment on the semiconductor wafer to diffuse the attached heavy metal into the semiconductor wafer;
The manufacturing method of the semiconductor element characterized by the above-mentioned.   2. The method of manufacturing a semiconductor device according to claim 1, wherein the step of injecting the inert element into the semiconductor wafer includes the step of amorphizing the position of the integrated depth from the surface of the semiconductor substrate.   The method for manufacturing a semiconductor device according to claim 1, wherein the inert element contains Ar (argon). 4. The Ar (argon) implantation includes a step of implanting at a dose of 1 * 10 < ¹⁴ > to 1 * 10 < ¹⁶ > / cm < ² > and an acceleration voltage of 20 to 160 KeV. A method for manufacturing a semiconductor device.   The method of manufacturing a semiconductor device according to claim 1, wherein the semiconductor device includes a fast recovery diode (fast diode).

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