JPH098062A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH098062A JPH098062A JP15460195A JP15460195A JPH098062A JP H098062 A JPH098062 A JP H098062A JP 15460195 A JP15460195 A JP 15460195A JP 15460195 A JP15460195 A JP 15460195A JP H098062 A JPH098062 A JP H098062A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor substrate
- thin film
- substrate
- semiconductor device
- back surface
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Links
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- Electrodes Of Semiconductors (AREA)
- Junction Field-Effect Transistors (AREA)
Abstract
Description
【0001】[0001]
【産業上の利用分野】本発明は半導体装置の製造方法に
係り、特に、高耐圧用または電力用半導体装置の製造方
法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a high breakdown voltage or power semiconductor device.
【0002】[0002]
【従来の技術】従来例として、例えば、図5(a)〜
(c)、図6(d)〜(f)に示す工程で作製される半
導体装置が挙げられる。まず、図5(a)に示すp型半
導体基板(例えばp型不純物濃度が1.0×1015/c
m3程度)21上の所定の位置に、n型拡散層23、p
型拡散層24、およびフィールド酸化膜22を形成する
〔図5(b)〕。次に、p型半導体基板21の裏面を、
所定の厚さだけグラインダ等により機械的に研削する
〔図5(c)〕。それから、p型半導体基板21の裏面
に、p型半導体基板21と同一導電型の不純物イオン注
入(例えばボロンイオン、40keV、5.0×1015
/cm2程度)25を行う〔図6(d)〕。次に、上記
不純物を拡散させるための熱処理(N2雰囲気中、約9
50℃、約20分)を行い、p型半導体基板21の裏面
表面に、高ドープp型拡散層26を形成する〔図6
(e)〕。その後、p型半導体基板21の表面の所定の
位置にアルミ配線27を形成し、最後に、p型半導体基
板21の裏面に電極となる金属薄膜〔裏面金属電極(T
i)〕28、金属薄膜〔裏面金属電極(Ni)〕29、
金属薄膜〔裏面金属電極(Ag)〕30を形成する〔図
6(f)〕。以上の方法により、p型半導体基板21
と、裏面の金属薄膜28、29、30の接合においてオ
ーミックの特性を得ることができ、金属薄膜28、2
9、30を裏面金属電極として用いることができる。こ
こで、金属−半導体接合について簡単に説明する。例え
ば、p型不純物濃度が1.0×1015/cm3程度のp型
半導体基板と金属薄膜の接合においてはショットキー障
壁が形成され、半導体と金属薄膜の界面部分の抵抗が高
くなり、低抵抗のオーミック接触が得られず、ショット
キー接触の特性を示す。したがって、この金属薄膜を裏
面電極として使用することは好ましくない。そこで、半
導体基板と金属薄膜との接合特性を向上させる方法、す
なわちオーミック特性(接触)が得られ、かつ抵抗を低
くするための一つの方法として、半導体基板裏面の不純
物濃度を上げ、トンネル効果を利用することで、低抵抗
のオーミック特性を得る方法がある。上述した従来例
は、このトンネル効果を利用したものである。しかし、
この従来例においては、半導体基板の裏面の研削工程が
存在する〔図5(c)〕。この工程は、半導体基板の厚
みを薄くすることによって、基板の熱抵抗等を低減させ
るために行われるものである。しかし、研削された半導
体基板は、研削工程以降の各工程において、基板の厚さ
が薄いことによる基板の割れや反りが起こり易くなると
いう問題がある。さらに、半導体基板の研削工程以降に
おいては、ドライエッチング工程における半導体基板の
温度が上昇しやすくなる。このため、ドライエッチング
工程では半導体基板の温度上昇を抑制するためにステー
ジを冷却している。しかし、研削後の半導体基板は薄く
反り易いと共に、研削面にある凹凸のためステージとの
密着性が悪くなり冷却効率が低下する。そのため、基板
を十分に冷却することができなくなるので、例えば、配
線パターン等を形成するためのレジストパターンの焦げ
や変形が生じ易くなる。特に、配線パターンの形成にお
いて緻密で信頼性の高い配線パターンが形成できないと
いう問題がある。また、裏面金属電極のオーミック特性
を得るために、不純物イオンを注入をし、これを拡散す
るために950℃の高温の熱処理を必要とすることか
ら、基板の裏面研削工程をアルミ配線の形成後には行え
ないという問題があった。2. Description of the Related Art As a conventional example, for example, FIG.
(C) and a semiconductor device manufactured in the steps shown in FIGS. 6D to 6F. First, a p-type semiconductor substrate (for example, a p-type impurity concentration of 1.0 × 10 15 / c shown in FIG.
m 3 ) at a predetermined position on the n-type diffusion layer 23, p
The type diffusion layer 24 and the field oxide film 22 are formed [FIG. 5 (b)]. Next, the back surface of the p-type semiconductor substrate 21 is
A predetermined thickness is mechanically ground by a grinder or the like [FIG. 5 (c)]. Then, impurity ions of the same conductivity type as the p-type semiconductor substrate 21 are implanted into the back surface of the p-type semiconductor substrate 21 (for example, boron ions, 40 keV, 5.0 × 10 15).
/ Cm 2 ) 25 (FIG. 6D). Next, a heat treatment for diffusing the impurities (in an N 2 atmosphere, about 9
50 ° C., about 20 minutes) to form a highly doped p-type diffusion layer 26 on the back surface of the p-type semiconductor substrate 21 (FIG. 6).
(E)]. Thereafter, aluminum wiring 27 is formed at a predetermined position on the front surface of the p-type semiconductor substrate 21, and finally, a metal thin film [rear surface metal electrode (T
i)] 28, metal thin film [backside metal electrode (Ni)] 29,
A metal thin film [backside metal electrode (Ag)] 30 is formed [FIG. 6 (f)]. By the above method, the p-type semiconductor substrate 21
And ohmic characteristics can be obtained in the bonding of the metal thin films 28, 29, 30 on the back surface.
9, 30 can be used as the back surface metal electrode. Here, the metal-semiconductor junction will be briefly described. For example, a Schottky barrier is formed at the junction between a p-type semiconductor substrate having a p-type impurity concentration of about 1.0 × 10 15 / cm 3 and a metal thin film, and the resistance at the interface between the semiconductor and the metal thin film becomes high. The ohmic contact of resistance is not obtained, and the characteristics of Schottky contact are exhibited. Therefore, it is not preferable to use this metal thin film as the back electrode. Therefore, as a method for improving the junction characteristics between the semiconductor substrate and the metal thin film, that is, one method for obtaining ohmic characteristics (contact) and reducing the resistance, the impurity concentration on the back surface of the semiconductor substrate is increased to improve the tunnel effect. There is a method of obtaining ohmic characteristics with low resistance by utilizing it. The above-mentioned conventional example utilizes this tunnel effect. But,
In this conventional example, there is a step of grinding the back surface of the semiconductor substrate [FIG. 5 (c)]. This step is performed to reduce the thermal resistance of the substrate by reducing the thickness of the semiconductor substrate. However, the ground semiconductor substrate has a problem that cracks or warpage of the substrate easily occur due to the thin thickness of the substrate in each step after the grinding step. Furthermore, after the semiconductor substrate grinding process, the temperature of the semiconductor substrate in the dry etching process is likely to rise. Therefore, in the dry etching process, the stage is cooled in order to suppress the temperature rise of the semiconductor substrate. However, the semiconductor substrate after grinding is thin and easily warped, and the unevenness on the ground surface reduces the adhesion to the stage and reduces the cooling efficiency. For this reason, the substrate cannot be cooled sufficiently, so that, for example, a resist pattern for forming a wiring pattern or the like is easily burnt or deformed. In particular, there is a problem that a dense and highly reliable wiring pattern cannot be formed in the formation of the wiring pattern. Further, in order to obtain the ohmic characteristics of the back surface metal electrode, it is necessary to implant impurity ions and to perform a high temperature heat treatment at 950 ° C. to diffuse the impurity ions. There was a problem that could not be done.
【0003】[0003]
【発明が解決しようとする課題】上述した従来例では、
半導体装置の製造工程において、半導体基板の裏面の研
削工程によって基板の厚さが薄くなり、そのため基板が
割れたり、反り易くなると共に、ドライエッチング工程
において冷却機能を備えたステージとの密着性が悪くな
り、冷却効率が低下するため、配線等のレジストパター
ンの焦げや変形などが生じ易くなり、緻密で信頼性の高
い配線パターンの形成が難しいという問題があった。ま
た、先願発明である特願平6−96321号に記載され
ている半導体装置は、図7(a)〜(c)、図8(d)
〜(e)に示す工程により作製される。まず、n型半導
体基板(例えば、n型不純物濃度が5.0×1018/c
m3程度)31〔図7(a)〕の所定の位置に、p型拡
散層33、n型拡散層34およびフィールド酸化膜32
およびアルミ配線35を形成する〔図7(b)〕。次
に、n型半導体基板31の裏面を所定の厚さだけ研削す
る〔図7(c)〕。それから、酸素プラズマ処理等によ
りn型半導体基板31の裏面に電荷を内在するプラズマ
酸化薄膜36を形成する〔図8(d)〕。そして、n型
半導体基板31の裏面に、金属薄膜〔裏面金属電極(T
i)〕37、金属薄膜〔裏面金属電極(Ni)〕38、
金属薄膜〔裏面金属電極(Ag)〕39を形成する〔図
8(e)〕。このようにすることにより、金属薄膜3
7、38、39とn型半導体基板31との接合において
オーミック特性を得ることができる。上記先願発明は、
上述した従来例とは異なり、不純物イオンを注入する工
程を用いないので、不純物を拡散するための高温の熱処
理は不要であり、また、半導体装置製造の最終工程で基
板の研削加工を行うこともできるので、基板の割れや反
り等、あるいはドライエッチング時の昇温によるレジス
トの焦げや変形等を防止することができる。しかし、上
記先願発明による方法は、基板の不純物濃度が高い場合
だけにしか適用できないという問題がある。例えば、実
務表面技術vol.32,No.2,1985,p.17〜p.21に掲載された
技術論文「SiとCr/NiCr/Ni3層構造の接触
抵抗」(北村、原田、横沢著)によると、Si基板とC
r/NiCr/Niの接合において、n型の場合では不
純物濃度が2.5×1018/cm3以下、p型の場合では
不純物濃度が3.0×1018/cm3以下では、それぞれ
接合の特性がオーミックにならないことが報告されてい
る。このように、半導体基板における不純物濃度が所定
の値以上でないと半導体基板と金属との間にオーミック
特性が得られないので、上記先願発明は不純物濃度の低
い半導体基板の場合には適用できないという問題があっ
た。In the above-mentioned conventional example,
In the manufacturing process of a semiconductor device, the thickness of the substrate is reduced due to the grinding process of the back surface of the semiconductor substrate, which easily causes the substrate to crack or warp, and the adhesion to the stage having a cooling function in the dry etching process is poor. However, since the cooling efficiency is lowered, the resist pattern such as wiring is liable to be scorched or deformed, which makes it difficult to form a precise and highly reliable wiring pattern. The semiconductor device disclosed in Japanese Patent Application No. 6-96321, which is the invention of the prior application, is shown in FIGS. 7 (a) to 7 (c) and 8 (d).
It is produced by the steps shown in to (e). First, an n-type semiconductor substrate (for example, an n-type impurity concentration of 5.0 × 10 18 / c) is used.
m 3 ) 31 [FIG. 7 (a)] at predetermined positions, the p-type diffusion layer 33, the n-type diffusion layer 34, and the field oxide film 32.
And aluminum wiring 35 is formed [FIG.7 (b)]. Next, the back surface of the n-type semiconductor substrate 31 is ground by a predetermined thickness [FIG. 7 (c)]. Then, a plasma oxide thin film 36 containing electric charges is formed on the back surface of the n-type semiconductor substrate 31 by oxygen plasma treatment or the like [FIG. 8 (d)]. Then, on the back surface of the n-type semiconductor substrate 31, a metal thin film [back surface metal electrode (T
i)] 37, metal thin film [backside metal electrode (Ni)] 38,
A metal thin film [backside metal electrode (Ag)] 39 is formed [FIG. 8 (e)]. By doing so, the metal thin film 3
Ohmic characteristics can be obtained in the junction between the 7, 38, 39 and the n-type semiconductor substrate 31. The above-mentioned prior invention is
Unlike the above-mentioned conventional example, since the step of implanting impurity ions is not used, high-temperature heat treatment for diffusing impurities is unnecessary, and the substrate may be ground in the final step of semiconductor device manufacturing. Therefore, it is possible to prevent the substrate from being cracked or warped, or the resist from being burnt or deformed due to a temperature rise during dry etching. However, the method according to the above-mentioned prior invention has a problem that it can be applied only when the impurity concentration of the substrate is high. For example, the technical paper “Contact resistance of Si and Cr / NiCr / Ni three-layer structure” published in Practical Surface Technology vol.32, No.2,1985, p.17-p.21 (written by Kitamura, Harada, Yokosawa) According to Si substrate and C
In the r / NiCr / Ni junction, when the impurity concentration is 2.5 × 10 18 / cm 3 or less in the case of n-type and the impurity concentration is 3.0 × 10 18 / cm 3 or less in the case of p-type, the junctions are respectively performed. It has been reported that the characteristics of are not ohmic. As described above, since the ohmic characteristics cannot be obtained between the semiconductor substrate and the metal unless the impurity concentration in the semiconductor substrate is equal to or higher than a predetermined value, the invention of the prior application cannot be applied in the case of a semiconductor substrate having a low impurity concentration. There was a problem.
【0004】本発明の目的は、上記従来技術および先願
発明における問題点を解消するものであって、半導体装
置の製造方法において、基板の研削工程を、半導体装置
の製造工程の最終工程で行うことにより、基板の割れ、
反りを抑止すると共に、ドライエッチング時の基板の昇
温を抑えてレジストパターンの変形や焦げを防止し、緻
密で信頼性の高い配線パターンを形成することができ、
かつ不純物濃度の低い半導体基板であっても、金属電極
と基板とが高性能のオーミック接合を形成することがで
きる半導体装置の製造方法を提供することにある。An object of the present invention is to solve the above problems in the prior art and the invention of the prior application. In the method of manufacturing a semiconductor device, the substrate grinding step is performed as the final step of the semiconductor device manufacturing step. This will cause the board to crack,
In addition to suppressing the warp, the temperature rise of the substrate during dry etching can be suppressed to prevent the resist pattern from being deformed or burnt, and a dense and highly reliable wiring pattern can be formed.
Further, it is an object of the present invention to provide a method of manufacturing a semiconductor device capable of forming a high-performance ohmic contact between a metal electrode and a substrate even if the semiconductor substrate has a low impurity concentration.
【0005】[0005]
【課題を解決するための手段】上記本発明の目的を達成
するために、本発明は特許請求の範囲に記載のような構
成とするものである。すなわち、本発明は請求項1に記
載のように、半導体基板の第1主面側に半導体装置の能
動領域を形成する工程と、上記半導体基板の第2主面側
を所定の厚さだけ研削する工程と、上記半導体基板の第
2主面側に、上記半導体装置の裏面電極となる金属薄膜
を形成する工程を少なくとも含む半導体装置の製造方法
において、上記半導体基板の第2主面側を研削する工程
の後に、上記半導体基板の第2主面と同一導電型の不純
物をイオン注入する工程と、上記半導体基板の第2主面
側に酸素プラズマ処理により酸化薄膜を形成する工程と
を少なくとも含む半導体装置の製造方法とするものであ
る。また、本発明は請求項2に記載のように、半導体基
板の第1主面側に半導体装置の能動領域を形成する工程
と、上記半導体基板の第2主面側を所定の厚さだけ研削
する工程と、上記半導体基板の第2主面側に上記半導体
装置の裏面電極となる金属薄膜を形成する工程を少なく
とも含む半導体装置の製造方法において、上記半導体基
板の第2主面側を研削する工程の後に、上記半導体基板
の第2主面と同一導電型の不純物をイオン注入する工程
と、上記半導体基板の第2主面側に酸素プラズマ処理に
より酸化薄膜を形成する工程と、上記酸化薄膜を除去す
る工程とを少なくとも含む半導体装置の製造方法とする
ものである。In order to achieve the above-mentioned object of the present invention, the present invention has a constitution as set forth in the claims. That is, according to the present invention, as described in claim 1, the step of forming the active region of the semiconductor device on the first main surface side of the semiconductor substrate and the second main surface side of the semiconductor substrate are ground by a predetermined thickness. And a step of forming a metal thin film to be a back surface electrode of the semiconductor device on the second main surface side of the semiconductor substrate, the second main surface side of the semiconductor substrate being ground. And the step of forming an oxide thin film on the second main surface side of the semiconductor substrate by oxygen plasma treatment after the step of performing an ion implantation of impurities of the same conductivity type as the second main surface of the semiconductor substrate. This is a method for manufacturing a semiconductor device. Further, according to the present invention, as described in claim 2, the step of forming the active region of the semiconductor device on the first main surface side of the semiconductor substrate and the second main surface side of the semiconductor substrate are ground by a predetermined thickness. And a step of forming a metal thin film to be a back surface electrode of the semiconductor device on the second main surface side of the semiconductor substrate, the second main surface side of the semiconductor substrate is ground. After the step, a step of ion-implanting impurities of the same conductivity type as the second main surface of the semiconductor substrate, a step of forming an oxide thin film on the second main surface side of the semiconductor substrate by oxygen plasma treatment, and the oxide thin film And a step of removing the semiconductor device.
【0006】[0006]
【作用】本発明者等は、特許請求の範囲の請求項1また
は請求項2に記載の半導体装置の製造方法とすることに
より、従来技術における問題点を解消すると共に、半導
体基板と金属薄膜との接合において高性能のオーミック
特性が得られることを、種々研究の結果見出したもので
ある。すなわち、請求項1に記載のように、半導体基板
表面に所定の能動領域を形成した後、半導体基板の裏面
を所定の厚さだけ除去し、半導体基板裏面に基板と同一
導電型の不純物をイオン注入し、高温の熱処理なしに、
続けて半導体基板裏面に酸素プラズマ処理等により酸化
薄膜を形成し、それから半導体基板裏面に金属薄膜を形
成するという製造工程を用いることにより、裏面電極と
なる金属薄膜と半導体基板との間の接合において高性能
のオーミック特性を得ることができる。これは、上記酸
素プラズマ処理により酸化薄膜が形成されると、半導体
基板裏面の極表面にトラップ(結晶欠陥)が形成される
ことと、上記イオン注入を行うと、その注入されたイオ
ンの活性化率は低いが半導体基板裏面のキャリア濃度が
高くなることにより、基板裏面の半導体と金属との接合
においてトンネル電流の確率が高くなり、そのため低抵
抗で高性能のオーミック接合が実現されるものと考えら
れる。したがって、半導体装置の製造過程において熱処
理を行わなくてもオーミック特性を得ることができるの
で、半導体基板の研削工程を半導体装置の製造工程の最
終工程で行うことが可能となり、基板の薄板化による割
れ、反り等を抑制することができ、さらにドライエッチ
ング工程における冷却機能付きのステージとの密着性が
悪くなり基板を十分に冷却できなくなるという問題が解
消されるので、ドライエッチング時の熱によるレジスト
パターンの焦げや変形などを防止することができ、特に
配線の形成において緻密で信頼性の高い配線パターンが
得られる。また請求項2に記載のように、半導体基板表
面に所定の能動領域を形成した後、半導体基板の裏面を
所定の厚さだけ除去し、半導体基板裏面に基板と同一導
電型の不純物をイオン注入し、高温の熱処理なしに、続
けて半導体基板裏面に酸素プラズマ処理等により酸化薄
膜を形成し、その酸化薄膜を希フッ酸等を用いて除去
し、それから半導体基板裏面に金属薄膜を形成するとい
う製造工程を用いるので、上記請求項1に示される共通
の効果に加えて、酸素プラズマ処理等により形成した酸
化薄膜を除去することにより、裏面電極となる金属薄膜
と半導体基板との間の接合抵抗をいっそう低くすること
ができ、極めて低い抵抗の高性能で信頼性の高いオーミ
ック接触を実現することができる。そして、上記請求項
1の場合と同様に、半導体装置の製造過程において熱処
理を行わなくてもオーミック特性を得ることができるこ
とから、半導体基板の研削工程を半導体装置の製造工程
の最終工程で行うことが可能となり、基板の割れ、反り
等を抑止することができる。さらに、ドライエッチング
工程における冷却機能付きのステージとの密着性が悪く
なり基板を十分に冷却できなくなるという問題も解消さ
れるので、レジストパターンの焦げや変形などの熱影響
を防止することができ、特に配線の形成において緻密で
信頼性の高い配線パターンが得られる。The present inventors solve the problems in the prior art by using the method of manufacturing a semiconductor device according to claim 1 or 2 of the claims, and at the same time, the semiconductor substrate and the metal thin film are formed. As a result of various studies, it has been found that high-performance ohmic characteristics can be obtained in the joining. That is, as described in claim 1, after forming a predetermined active region on the front surface of the semiconductor substrate, the back surface of the semiconductor substrate is removed by a predetermined thickness, and impurities of the same conductivity type as the substrate are ion-deposited on the back surface of the semiconductor substrate. Injection, without high temperature heat treatment,
By continuously using a manufacturing process of forming an oxide thin film on the back surface of the semiconductor substrate by oxygen plasma treatment or the like, and then forming a metal thin film on the back surface of the semiconductor substrate, in the bonding between the metal thin film to be the back surface electrode and the semiconductor substrate. High-performance ohmic characteristics can be obtained. This is because when an oxide thin film is formed by the above-mentioned oxygen plasma treatment, a trap (crystal defect) is formed on the extreme surface of the back surface of the semiconductor substrate, and when the above-mentioned ion implantation is performed, the implanted ions are activated. Although the ratio is low, the carrier concentration on the back surface of the semiconductor substrate is high, so that the probability of tunnel current increases at the junction between the semiconductor and the metal on the back surface of the substrate, and it is thought that a high-performance ohmic junction with low resistance will be realized. To be Therefore, since ohmic characteristics can be obtained without performing heat treatment in the process of manufacturing the semiconductor device, it becomes possible to perform the grinding process of the semiconductor substrate in the final process of the manufacturing process of the semiconductor device, and the cracking due to the thinning of the substrate. Since the problem that the substrate cannot be sufficiently cooled because the adhesion with the stage with a cooling function in the dry etching process is reduced, the resist pattern due to heat during dry etching can be solved. It is possible to prevent charring and deformation of the wiring, and in particular, it is possible to obtain a dense and highly reliable wiring pattern in the formation of wiring. Further, as described in claim 2, after forming a predetermined active region on the front surface of the semiconductor substrate, the back surface of the semiconductor substrate is removed by a predetermined thickness, and impurities of the same conductivity type as the substrate are ion-implanted into the back surface of the semiconductor substrate. Then, without heat treatment at high temperature, an oxide thin film is continuously formed on the back surface of the semiconductor substrate by oxygen plasma treatment, etc., the oxide thin film is removed using dilute hydrofluoric acid, and then a metal thin film is formed on the back surface of the semiconductor substrate. Since the manufacturing process is used, in addition to the common effect described in claim 1, by removing the oxide thin film formed by oxygen plasma treatment or the like, the junction resistance between the metal thin film to be the back surface electrode and the semiconductor substrate is increased. Can be made even lower, and high-performance and highly reliable ohmic contact with extremely low resistance can be realized. As in the case of claim 1, since the ohmic characteristics can be obtained without performing heat treatment in the manufacturing process of the semiconductor device, the grinding step of the semiconductor substrate is performed in the final step of the manufacturing process of the semiconductor device. It is possible to prevent the substrate from cracking or warping. Furthermore, since the problem that the adhesion to the stage with a cooling function in the dry etching process is deteriorated and the substrate cannot be cooled sufficiently, it is possible to prevent thermal effects such as scorching and deformation of the resist pattern, Particularly in the formation of wiring, a dense and highly reliable wiring pattern can be obtained.
【0007】[0007]
【実施例】以下、本発明の一実施例を挙げ、図面を用い
てさらに詳細に説明する。 〈実施例1〉図1(a)〜(c)、図2(d)〜(f)
は、本実施例で例示する半導体装置の製造過程を示す工
程図である。始めに、図1(a)に示すp型半導体基板
(例えばp型シリコンの場合、不純物濃度1.0×10
15/cm3程度)1上の所定の位置に、n型拡散層3、
p型拡散層4、フィールド酸化膜2、アルミ配線5等か
らなる能動領域を形成する〔図1(b)〕。それから、
p型半導体基板1の裏面を機械的に研削する〔図1
(c)〕。次に、p型半導体基板1の裏面に、p型半導
体基板1と同一導電型の不純物イオン注入(例えばボロ
ンイオン、40keV、5.0×1015/cm2)6を行
う〔図2(d)〕。それから、p型半導体基板1の裏面
に、酸素プラズマ処理(例えばO2、1Torr、40
0W、5min程度の条件を用いて処理する)等により
プラズマ酸化薄膜7を形成する〔図2(e)〕。 次
に、p型半導体基板1の裏面に、電極となる金属薄膜
〔裏面金属電極(Ti)〕8、金属薄膜〔裏面金属電極
(Ni)〕9、〔裏面金属電極(Ag)〕10を蒸着す
る。このように、半導体装置の製造過程において熱処理
を行わなくてもオーミック特性を得ることができるの
で、半導体基板を薄板化する研削工程を半導体装置の製
造工程の最終工程で行うことが可能となり、基板裏面の
研削後の工程を短縮することができ、基板の割れ、反り
等を抑止することができる。さらに、ドライエッチング
工程における冷却機能付きのステージとの密着性が悪く
なり基板を十分に冷却できなくなるという問題も解消さ
れるので、レジストパターンの焦げや変形などの熱影響
を防止することができ、特に配線の形成において緻密で
信頼性の高い配線パターンが得られる。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below in more detail with reference to the drawings. <Example 1> FIGS. 1A to 1C and 2D to 2F.
FIG. 4A is a process diagram showing a manufacturing process of a semiconductor device exemplified in the present embodiment. First, a p-type semiconductor substrate shown in FIG. 1A (for example, in the case of p-type silicon, an impurity concentration of 1.0 × 10
15 / cm 3 ) at a predetermined position on the n-type diffusion layer 3,
An active region including the p-type diffusion layer 4, the field oxide film 2, the aluminum wiring 5 and the like is formed [FIG. 1 (b)]. then,
The back surface of the p-type semiconductor substrate 1 is mechanically ground [Fig. 1
(C)]. Next, on the back surface of the p-type semiconductor substrate 1, impurity ion implantation (for example, boron ions, 40 keV, 5.0 × 10 15 / cm 2 ) 6 of the same conductivity type as the p-type semiconductor substrate 1 is performed [FIG. )]. Then, on the back surface of the p-type semiconductor substrate 1, an oxygen plasma treatment (for example, O 2 , 1 Torr, 40
The plasma oxide thin film 7 is formed by, for example, processing under conditions of 0 W and 5 minutes (FIG. 2E). Next, on the back surface of the p-type semiconductor substrate 1, a metal thin film [back surface metal electrode (Ti)] 8, a metal thin film [back surface metal electrode (Ni)] 9, and [back surface metal electrode (Ag)] 10 are vapor-deposited. To do. In this way, since ohmic characteristics can be obtained without performing heat treatment in the manufacturing process of the semiconductor device, it becomes possible to perform the grinding process for thinning the semiconductor substrate in the final process of the manufacturing process of the semiconductor device. The process after grinding the back surface can be shortened, and cracks and warpage of the substrate can be suppressed. Furthermore, since the problem that the adhesion to the stage with a cooling function in the dry etching process is deteriorated and the substrate cannot be cooled sufficiently, it is possible to prevent thermal effects such as scorching and deformation of the resist pattern, Particularly in the formation of wiring, a dense and highly reliable wiring pattern can be obtained.
【0008】〈実施例2〉図3(a)〜(d)、図4
(e)〜(g)は、本実施例で例示する半導体装置の製
造過程を示す工程図である。本実施例においては、能動
領域を形成し、p型半導体基板11の裏面を研削し、p
型半導体基板11と同一導電型の不純物イオン注入16
し、その後、酸素プラズマ処理等により、半導体基板1
1の裏面に、プラズマ酸化薄膜17を形成〔図4
(e)〕するところまでは、上記の実施例1と同様の工
程で行った。それから、p型半導体基板11の裏面に形
成されたプラズマ酸化薄膜17を希フッ酸により除去し
〔図4(f)〕、その後、金属薄膜〔裏面金属電極(T
i)〕18、金属薄膜〔裏面金属電極(Ni)〕19、
金属薄膜〔裏面金属電極(Ag)〕20を蒸着して、そ
れぞれの裏面金属電極を形成した〔図4(g)〕。この
ように、p型半導体基板11の裏面に形成されたプラズ
マ酸化薄膜17を除去した後、それぞれの裏面金属電極
を形成するので、上記実施例1よりも、裏面金属電極と
基板との接合抵抗が低減され、低抵抗で高性能のオーミ
ック特性が得られる。上記本発明の実施例に示すよう
に、半導体基板表面にイオン注入し、その基板表面を酸
素プラズマ処理により酸化薄膜を形成し、その上に金属
薄膜を形成することによって、高温の熱処理を行うこと
なしに半導体基板と金属薄膜の接合においてオーミック
特性が得られる。その理由は明確ではないが、次のよう
に考えられる。まず、酸素プラズマ処理により酸化薄膜
を形成すると、半導体基板の極表面にトラップ(結晶欠
陥)が形成される。また、イオン注入を行うと、その注
入されたイオンによる活性化率は低いものの半導体基板
のキャリア濃度が高くなる。この二つの現象が相まっ
て、基板表面の半導体と金属との接合において、トンネ
ル電流の確率が高くなるものと考えられる。図9(a)
は、従来のイオン注入および酸素プラズマ処理を行わな
い場合の金属(電極)−半導体基板(p型)接触のエネ
ルギーバンド図を示し、図9(b)は、本発明の実施例
であるイオン注入および酸素プラズマ処理を行った場合
の金属(電極)−半導体基板(p型)接触のエネルギー
バンド図を示す、図9(b)に示すように、半導体基板
の極表面にトラップ(結晶欠陥×印)が形成され、その
結果、半導体基板と金属との接合においてトンネル電流
の確率が高くなり、そのため良好なオーミック特性が得
られるものと考えられる。ここで、酸素プラズマ処理に
よる酸化薄膜の形成は不純物イオンの注入工程の後に行
っていたが、その前に行うことも可能である。図10
は、イオン注入、酸素プラズマ処理、熱処理の各工程に
おいて、半導体基板と金属薄膜との接合の特性について
実験結果をまとめたものである。ここで、半導体基板は
比抵抗10Ωcmのp型基板を用いた。また、注入した
イオンはボロンイオンで、打ち込みエネルギー40ke
V、濃度5.0×1015/cm2の条件とした。なお、図
10において、○印は、イオン注入、酸素プラズマ処
理、熱処理を行い、オーミック特性が得られたことを表
わし、×印は、イオン注入、熱処理を行わず、オーミッ
ク特性が得られなかったことを表わしている。そして、
条件No.1は、イオン注入、酸素プラズマ処理、熱処
理を行った場合で、オーミック特性が得られたことを示
し、条件No.2は、イオン注入、酸素プラズマ処理を
行い、熱処理を行わない場合を示し、高温の熱処理を行
わなくても半導体基板と金属薄膜との接合においてオー
ミック特性が得られることを示している。条件No.3
は、酸素プラズマ処理のみ行い、イオン注入、熱処理を
行わない場合で、イオン注入を行わないとオーミック特
性が得られないことを示している。図11〜図13は、
図10に示した条件No.1、2または3の処理を行っ
た場合の半導体基板と金属薄膜の接合領域における電流
(I)−電圧(V)特性を示したものである。図11
は、図10における条件No.1で、イオン注入、酸素
プラズマ処理、熱処理を行った場合の電流−電圧特性を
示すもので、I−V特性は直線的で、かつ正負の電圧に
対して対称的であり、理想的なオーミック特性を示して
いる。また、図12は、図10における条件No.2
で、イオン注入、酸素プラズマ処理を行い、熱処理を行
わない場合であり、高温の熱処理を行わなくても半導体
基板と金属薄膜との接合において、上記図11の場合と
同様に、理想的なオーミック特性が得られることを示し
ている。また、図13は、図10における条件No.3
で、酸素プラズマ処理のみ行い、イオン注入、熱処理を
行わない場合であり、イオン注入を行わないとオーミッ
ク接触を示すI−V特性が得られないことを示してい
る。<Embodiment 2> FIGS. 3 (a) to 3 (d) and FIG.
(E)-(g) is process drawing which shows the manufacturing process of the semiconductor device illustrated by a present Example. In this embodiment, an active region is formed, the back surface of the p-type semiconductor substrate 11 is ground, and p
Ion implantation of the same conductivity type as the semiconductor substrate 11
Then, the semiconductor substrate 1 is subjected to oxygen plasma treatment or the like.
1. A plasma oxide thin film 17 is formed on the back surface of FIG.
Up to the step (e)], the same steps as in Example 1 were performed. Then, the plasma oxide thin film 17 formed on the back surface of the p-type semiconductor substrate 11 is removed by dilute hydrofluoric acid [FIG. 4 (f)], and then a metal thin film [back surface metal electrode (T
i)] 18, metal thin film [backside metal electrode (Ni)] 19,
A metal thin film [backside metal electrode (Ag)] 20 was vapor-deposited to form each backside metal electrode [FIG. 4 (g)]. As described above, since the back surface metal electrode is formed after removing the plasma oxide thin film 17 formed on the back surface of the p-type semiconductor substrate 11, the bonding resistance between the back surface metal electrode and the substrate is larger than that in the first embodiment. And high resistance ohmic characteristics with low resistance. As shown in the above embodiments of the present invention, high temperature heat treatment is performed by ion-implanting a semiconductor substrate surface, forming an oxide thin film on the substrate surface by oxygen plasma treatment, and forming a metal thin film on the oxide thin film. Without it, ohmic characteristics can be obtained in the joining of the semiconductor substrate and the metal thin film. The reason is not clear, but it is considered as follows. First, when an oxide thin film is formed by oxygen plasma treatment, traps (crystal defects) are formed on the extreme surface of the semiconductor substrate. When ion implantation is performed, the carrier concentration of the semiconductor substrate increases although the activation rate by the implanted ions is low. It is considered that these two phenomena combine to increase the probability of tunnel current at the junction between the semiconductor on the substrate surface and the metal. FIG. 9 (a)
Shows an energy band diagram of metal (electrode) -semiconductor substrate (p-type) contact when conventional ion implantation and oxygen plasma treatment are not performed, and FIG. 9B is an ion implantation which is an embodiment of the present invention. 9B shows an energy band diagram of metal (electrode) -semiconductor substrate (p-type) contact when oxygen plasma treatment is performed, and as shown in FIG. 9B, traps (crystal defects x marks) are formed on the extreme surface of the semiconductor substrate. ) Is formed, and as a result, the probability of tunneling current increases at the junction between the semiconductor substrate and the metal, and it is considered that good ohmic characteristics are obtained. Here, the formation of the oxide thin film by the oxygen plasma treatment was performed after the step of implanting the impurity ions, but it may be performed before that. FIG.
Is a summary of experimental results regarding the characteristics of bonding between the semiconductor substrate and the metal thin film in each of the steps of ion implantation, oxygen plasma treatment, and heat treatment. Here, a p-type substrate having a specific resistance of 10 Ωcm was used as the semiconductor substrate. The implanted ions are boron ions, and the implantation energy is 40 ke.
The conditions were V and a concentration of 5.0 × 10 15 / cm 2 . In FIG. 10, the mark ∘ indicates that ohmic characteristics were obtained by performing ion implantation, oxygen plasma treatment, and heat treatment, and the mark × indicates that ohmic characteristics were not obtained because neither ion implantation nor heat treatment was performed. It means that. And
Condition No. 1 shows that ohmic characteristics were obtained when ion implantation, oxygen plasma treatment, and heat treatment were performed, and condition No. 2 showed that ion implantation, oxygen plasma treatment was performed, and heat treatment was not performed. It is shown that ohmic characteristics can be obtained in the bonding between the semiconductor substrate and the metal thin film without performing high temperature heat treatment. Condition No. 3
Indicates that when only oxygen plasma treatment is performed and ion implantation and heat treatment are not performed, ohmic characteristics cannot be obtained without ion implantation. 11 to 13 show
11 shows current (I) -voltage (V) characteristics in the junction region between the semiconductor substrate and the metal thin film when the treatment of condition No. 1, 2 or 3 shown in FIG. 10 is performed. FIG.
10 shows current-voltage characteristics when ion implantation, oxygen plasma treatment, and heat treatment are performed under condition No. 1 in FIG. 10, the IV characteristics are linear and symmetrical with respect to positive and negative voltages. And shows ideal ohmic characteristics. Further, FIG. 12 shows the condition No. 2 in FIG.
In the case where the ion implantation and the oxygen plasma treatment are performed and the heat treatment is not performed, an ideal ohmic contact is obtained in the bonding between the semiconductor substrate and the metal thin film without performing the high temperature heat treatment, as in the case of FIG. It shows that the characteristics can be obtained. Further, FIG. 13 shows the condition No. 3 in FIG.
2 shows that only the oxygen plasma treatment is performed and the ion implantation and the heat treatment are not performed, and the IV characteristics showing ohmic contact cannot be obtained without ion implantation.
【0009】[0009]
【発明の効果】以上詳細に説明したように、本発明の半
導体装置の製造方法は、以下に示す効果がある。すなわ
ち、請求項1に記載のように、半導体基板表面に所定の
能動領域を形成した後、半導体基板の裏面を所定の厚さ
だけ除去し、半導体基板裏面に基板と同一導電型の不純
物をイオン注入し、高温の熱処理なしに、続けて半導体
基板裏面に酸素プラズマ処理等により酸化薄膜を形成
し、それから半導体基板裏面に金属薄膜を形成するとい
う製造工程を用いることにより、裏面電極となる金属薄
膜と半導体基板との間の接合において高性能のオーミッ
ク特性を得ることができる。これは、上記酸素プラズマ
処理により酸化薄膜が形成されると、半導体基板裏面の
極表面にトラップ(結晶欠陥)が形成されることと、上
記イオン注入を行うと、その注入されたイオンの活性化
率は低いが半導体基板裏面のキャリア濃度が高くなるこ
とにより、基板裏面の半導体と金属との接合においてト
ンネル電流の確率が高くなり、そのため低抵抗で高性能
のオーミック接合が実現されるものと考えられる。した
がって、半導体装置の製造過程において熱処理を行わな
くてもオーミック特性を得ることができるので、半導体
基板の研削工程を半導体装置の製造工程の最終工程で行
うことができるので、基板の薄板化による割れ、反り等
を抑制することができ、さらにドライエッチング工程に
おける冷却機能付きのステージとの密着性が悪くなり基
板を十分に冷却できなくなるという問題がなくなるの
で、レジストパターンの焦げや変形などの熱影響を防止
することができ、特に配線の形成において緻密で信頼性
の高い配線パターンが得られる。また請求項2に記載の
ように、半導体基板表面に所定の能動領域を形成した
後、半導体基板の裏面を所定の厚さだけ除去し、半導体
基板裏面に基板と同一導電型の不純物をイオン注入し、
高温の熱処理なしに、続けて半導体基板裏面に酸素プラ
ズマ処理等により酸化薄膜を形成し、その酸化薄膜を希
フッ酸等を用いて除去し、それから半導体基板裏面に金
属薄膜を形成するという製造工程を用いるので、上記請
求項1に示される共通の効果に加えて、酸素プラズマ処
理等により形成した酸化薄膜を除去するので、裏面電極
となる金属薄膜と半導体基板との間の接合の抵抗がいっ
そう低くなり、極めて低い抵抗の高性能で信頼性の高い
オーミック接触を実現することができる。そして、上記
請求項1の場合と同様に、半導体装置の製造過程におい
て熱処理を行わなくてもオーミック特性を得ることがで
きることから、半導体基板の研削工程を半導体装置の製
造工程の最終工程で行うことができるので、基板の割
れ、反り等を抑止することが可能であり、さらにドライ
エッチング工程における冷却機能付きのステージとの密
着性が悪くなり基板を十分に冷却できなくなるという問
題がなくなるので、レジストパターンの焦げや変形など
の熱影響を防止することができ、特に配線の形成におい
て緻密で信頼性の高い配線パターンが得られる。As described in detail above, the method of manufacturing a semiconductor device of the present invention has the following effects. That is, as described in claim 1, after forming a predetermined active region on the front surface of the semiconductor substrate, the back surface of the semiconductor substrate is removed by a predetermined thickness, and impurities of the same conductivity type as the substrate are ion-deposited on the back surface of the semiconductor substrate. By using a manufacturing process in which a thin oxide film is formed on the back surface of the semiconductor substrate by oxygen plasma treatment, etc., and then a metal thin film is formed on the back surface of the semiconductor substrate without performing heat treatment at high temperature, a metal thin film serving as a back electrode is formed. High-performance ohmic characteristics can be obtained in the junction between the semiconductor substrate and the semiconductor substrate. This is because when an oxide thin film is formed by the above-mentioned oxygen plasma treatment, a trap (crystal defect) is formed on the extreme surface of the back surface of the semiconductor substrate, and when the above-mentioned ion implantation is performed, the implanted ions are activated. Although the ratio is low, the carrier concentration on the back surface of the semiconductor substrate is high, so that the probability of tunnel current increases at the junction between the semiconductor and the metal on the back surface of the substrate, and it is thought that a high-performance ohmic junction with low resistance will be realized. To be Therefore, since ohmic characteristics can be obtained without performing heat treatment in the manufacturing process of the semiconductor device, the grinding process of the semiconductor substrate can be performed in the final process of the manufacturing process of the semiconductor device. , The warp, etc. can be suppressed, and further, the problem that the adhesion with the stage with a cooling function in the dry etching process deteriorates and the substrate cannot be cooled sufficiently, so there is no thermal effect such as burning or deformation of the resist pattern. Can be prevented, and a dense and highly reliable wiring pattern can be obtained especially in the formation of wiring. Further, as described in claim 2, after forming a predetermined active region on the front surface of the semiconductor substrate, the back surface of the semiconductor substrate is removed by a predetermined thickness, and impurities of the same conductivity type as the substrate are ion-implanted into the back surface of the semiconductor substrate. Then
A manufacturing process in which an oxide thin film is continuously formed on the back surface of a semiconductor substrate by oxygen plasma treatment, etc. without high-temperature heat treatment, the oxide thin film is removed using dilute hydrofluoric acid, and then a metal thin film is formed on the back surface of the semiconductor substrate. In addition to the common effect described in claim 1, since the oxide thin film formed by the oxygen plasma treatment or the like is removed, the resistance of the junction between the metal thin film to be the back electrode and the semiconductor substrate is further improved. High performance and highly reliable ohmic contact with low resistance can be realized. As in the case of claim 1, since the ohmic characteristics can be obtained without performing heat treatment in the manufacturing process of the semiconductor device, the grinding step of the semiconductor substrate is performed in the final step of the manufacturing process of the semiconductor device. Therefore, it is possible to prevent the substrate from cracking, warping, and the like, and the problem that the adhesion with the stage with a cooling function in the dry etching process deteriorates and the substrate cannot be cooled sufficiently is eliminated. It is possible to prevent thermal effects such as scorching and deformation of the pattern, and a dense and highly reliable wiring pattern can be obtained especially in the formation of the wiring.
【図1】本発明の実施例1において例示した半導体装置
の作製過程を示す工程図。FIG. 1 is a process drawing showing a manufacturing process of a semiconductor device exemplified in a first embodiment of the present invention.
【図2】本発明の実施例1において例示した半導体装置
の作製過程を示す工程図。2A to 2C are process diagrams showing a manufacturing process of the semiconductor device illustrated in the first embodiment of the present invention.
【図3】本発明の実施例2において例示した半導体装置
の作製過程を示す工程図。3A to 3D are process diagrams showing a manufacturing process of the semiconductor device illustrated in the second embodiment of the present invention.
【図4】本発明の実施例2において例示した半導体装置
の作製過程を示す工程図。4A to 4C are process diagrams showing a manufacturing process of the semiconductor device illustrated in the second embodiment of the present invention.
【図5】従来の半導体装置の作製過程を示す工程図。5A to 5C are process diagrams showing a manufacturing process of a conventional semiconductor device.
【図6】従来の半導体装置の作製過程を示す工程図。6A to 6C are process diagrams showing a manufacturing process of a conventional semiconductor device.
【図7】先願発明(特願平6−96321号)の半導体
装置の作製過程を示す工程図。FIG. 7 is a process drawing showing a process for manufacturing a semiconductor device of the prior invention (Japanese Patent Application No. 6-96321).
【図8】先願発明(特願平6−96321号)の半導体
装置の作製過程を示す工程図。FIG. 8 is a process drawing showing a process of manufacturing a semiconductor device of a prior invention (Japanese Patent Application No. 6-96321).
【図9】本発明の実施例において例示した半導体装置
(b)の金属(電極)−半導体基板(p型)接触のエネ
ルギーバンド図および従来の半導体装置(a)の金属
(電極)−半導体基板(p型)接触のエネルギーバンド
図。FIG. 9 is an energy band diagram of a metal (electrode) -semiconductor substrate (p-type) contact of the semiconductor device (b) illustrated in the example of the present invention and a metal (electrode) -semiconductor substrate of the conventional semiconductor device (a). Energy band diagram of (p-type) contact.
【図10】本発明の実施例において例示した各処理条件
における半導体基板と金属薄膜とのオーミック接合特性
を示す図。FIG. 10 is a diagram showing ohmic contact characteristics between a semiconductor substrate and a metal thin film under each processing condition exemplified in the example of the present invention.
【図11】本発明の実施例において例示した半導体基板
と金属薄膜との接合における電流−電圧特性(オーミッ
ク特性)を示すグラフ。FIG. 11 is a graph showing current-voltage characteristics (ohmic characteristics) at the junction between the semiconductor substrate and the metal thin film exemplified in the example of the present invention.
【図12】本発明の実施例において例示した半導体基板
と金属薄膜との接合における電流−電圧特性(オーミッ
ク特性)を示すグラフ。FIG. 12 is a graph showing current-voltage characteristics (ohmic characteristics) at the junction between the semiconductor substrate and the metal thin film exemplified in the example of the present invention.
【図13】比較例として示した半導体基板と金属薄膜と
の接合における電流−電圧特性を示すグラフ。FIG. 13 is a graph showing current-voltage characteristics in a junction between a semiconductor substrate and a metal thin film shown as a comparative example.
1…p型半導体基板 2…フィールド酸化膜 3
…n型拡散層 4…p型拡散層 5…アルミ配線 6…不純物イオン
(ボロンイオン)注入 7…プラズマ酸化薄膜 8…金属薄膜〔裏面金属
電極(Ti)〕 9…金属薄膜〔裏面金属電極(Ni)〕 10…金属薄膜〔裏面金属電極(Ag)〕 11
…p型半導体基板 12…フィールド酸化膜 13…n型拡散層 14
…p型拡散層 15…アルミ配線 16…不純物イオン(ボロンイオ
ン)注入 17…プラズマ酸化薄膜 18…金属薄膜〔裏面金
属電極(Ti)〕 19…金属薄膜〔裏面金属電極(Ni)〕 20…金属薄膜〔裏面金属電極(Ag)〕 21…p型半導体基板 22…フィールド酸化膜 23
…n型拡散層 24…p型拡散層 25…不純物イオン(ボロンイ
オン)注入 26…高ドープp型拡散層 27…アルミ配線 28…金属薄膜〔裏面金属電極(Ti)〕 29…金属薄膜〔裏面金属電極(Ni)〕 30…金属薄膜〔裏面金属電極(Ag)〕 31
…n型半導体基板 32…フィールド酸化膜 33…p型拡散層 34
…n型拡散層 35…アルミ配線 36…プラズマ酸化薄膜 37…金属薄膜〔裏面金属電極(Ti)〕 38…金属薄膜〔裏面金属電極(Ni)〕 39…金属薄膜〔裏面金属電極(Ag)〕1 ... p-type semiconductor substrate 2 ... field oxide film 3
... n-type diffusion layer 4 ... p-type diffusion layer 5 ... aluminum wiring 6 ... impurity ion (boron ion) implantation 7 ... plasma oxide thin film 8 ... metal thin film [backside metal electrode (Ti)] 9 ... metal thin film [backside metal electrode ( Ni)] 10 ... Metal thin film [Backside metal electrode (Ag)] 11
... p-type semiconductor substrate 12 ... field oxide film 13 ... n-type diffusion layer 14
... p-type diffusion layer 15 ... aluminum wiring 16 ... impurity ion (boron ion) implantation 17 ... plasma oxide thin film 18 ... metal thin film [rear surface metal electrode (Ti)] 19 ... metal thin film [rear surface metal electrode (Ni)] 20 ... metal Thin film [Backside metal electrode (Ag)] 21 ... P-type semiconductor substrate 22 ... Field oxide film 23
... n-type diffusion layer 24 ... p-type diffusion layer 25 ... impurity ion (boron ion) implantation 26 ... highly doped p-type diffusion layer 27 ... aluminum wiring 28 ... metal thin film [back surface metal electrode (Ti)] 29 ... metal thin film [back surface] Metal electrode (Ni)] 30 ... Metal thin film [Backside metal electrode (Ag)] 31
... n-type semiconductor substrate 32 ... field oxide film 33 ... p-type diffusion layer 34
... n-type diffusion layer 35 ... aluminum wiring 36 ... plasma oxide thin film 37 ... metal thin film [rear surface metal electrode (Ti)] 38 ... metal thin film [rear surface metal electrode (Ni)] 39 ... metal thin film [rear surface metal electrode (Ag)]
───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.6 識別記号 庁内整理番号 FI 技術表示箇所 H01L 29/808 ──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. 6 Identification code Agency reference number FI Technical display location H01L 29/808
Claims (2)
動領域を形成する工程と、上記半導体基板の第2主面側
を所定の厚さだけ研削する工程と、上記半導体基板の第
2主面側に、上記半導体装置の裏面電極となる金属薄膜
を形成する工程を少なくとも含む半導体装置の製造方法
において、 上記半導体基板の第2主面側を研削する工程の後に、上
記半導体基板の第2主面と同一導電型の不純物をイオン
注入する工程と、 上記半導体基板の第2主面側に酸素プラズマ処理により
酸化薄膜を形成する工程とを少なくとも含むことを特徴
とする半導体装置の製造方法。1. A step of forming an active region of a semiconductor device on a first main surface side of a semiconductor substrate, a step of grinding a second main surface side of the semiconductor substrate by a predetermined thickness, and a first step of the semiconductor substrate. In a method of manufacturing a semiconductor device, which includes at least a step of forming a metal thin film to be a back surface electrode of the semiconductor device on the second main surface side, after the step of grinding the second main surface side of the semiconductor substrate, Manufacturing of a semiconductor device including at least a step of ion-implanting impurities of the same conductivity type as the second main surface and a step of forming an oxide thin film on the second main surface side of the semiconductor substrate by oxygen plasma treatment. Method.
動領域を形成する工程と、上記半導体基板の第2主面側
を所定の厚さだけ研削する工程と、上記半導体基板の第
2主面側に上記半導体装置の裏面電極となる金属薄膜を
形成する工程を少なくとも含む半導体装置の製造方法に
おいて、 上記半導体基板の第2主面側を研削する工程の後に、上
記半導体基板の第2主面と同一導電型の不純物をイオン
注入する工程と、 上記半導体基板の第2主面側に酸素プラズマ処理により
酸化薄膜を形成する工程と、 上記酸化薄膜を除去する工程とを少なくとも含むことを
特徴とする半導体装置の製造方法。2. A step of forming an active region of a semiconductor device on a first main surface side of a semiconductor substrate, a step of grinding a second main surface side of the semiconductor substrate by a predetermined thickness, and a second step of the semiconductor substrate. In a method of manufacturing a semiconductor device, which includes at least a step of forming a metal thin film to be a back surface electrode of the semiconductor device on the second main surface side, after the step of grinding the second main surface side of the semiconductor substrate, 2 at least including a step of implanting impurities of the same conductivity type as the main surface, a step of forming an oxide thin film on the second main surface side of the semiconductor substrate by oxygen plasma treatment, and a step of removing the oxide thin film. A method for manufacturing a semiconductor device, comprising:
Priority Applications (1)
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JP15460195A JP3289550B2 (en) | 1995-06-21 | 1995-06-21 | Method for manufacturing semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP15460195A JP3289550B2 (en) | 1995-06-21 | 1995-06-21 | Method for manufacturing semiconductor device |
Publications (2)
Publication Number | Publication Date |
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JPH098062A true JPH098062A (en) | 1997-01-10 |
JP3289550B2 JP3289550B2 (en) | 2002-06-10 |
Family
ID=15587755
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JP15460195A Expired - Fee Related JP3289550B2 (en) | 1995-06-21 | 1995-06-21 | Method for manufacturing semiconductor device |
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JP (1) | JP3289550B2 (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2010082476A1 (en) | 2009-01-16 | 2010-07-22 | 昭和電工株式会社 | Method for manufacturing semiconductor element, semiconductor element and semiconductor device |
DE112017005206T5 (en) | 2016-10-13 | 2019-07-04 | Mitsubishi Electric Corporation | METHOD FOR PRODUCING A SEMICONDUCTOR UNIT |
CN109997215A (en) * | 2017-01-24 | 2019-07-09 | 新电元工业株式会社 | The manufacturing method of semiconductor device |
-
1995
- 1995-06-21 JP JP15460195A patent/JP3289550B2/en not_active Expired - Fee Related
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2010082476A1 (en) | 2009-01-16 | 2010-07-22 | 昭和電工株式会社 | Method for manufacturing semiconductor element, semiconductor element and semiconductor device |
US8679882B2 (en) | 2009-01-16 | 2014-03-25 | Show A Denko K.K. | Method of manufacturing semiconductor device, semiconductor device, and semiconductor apparatus |
DE112017005206T5 (en) | 2016-10-13 | 2019-07-04 | Mitsubishi Electric Corporation | METHOD FOR PRODUCING A SEMICONDUCTOR UNIT |
US10665459B2 (en) | 2016-10-13 | 2020-05-26 | Mitsubishi Electric Corporation | Method for manufacturing semiconductor device |
CN109997215A (en) * | 2017-01-24 | 2019-07-09 | 新电元工业株式会社 | The manufacturing method of semiconductor device |
Also Published As
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JP3289550B2 (en) | 2002-06-10 |
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