JP2001210654A - Method of manufacturing semiconductor film having characteristic in withstand voltage - Google Patents

Method of manufacturing semiconductor film having characteristic in withstand voltage

Info

Publication number
JP2001210654A
JP2001210654A JP2000020153A JP2000020153A JP2001210654A JP 2001210654 A JP2001210654 A JP 2001210654A JP 2000020153 A JP2000020153 A JP 2000020153A JP 2000020153 A JP2000020153 A JP 2000020153A JP 2001210654 A JP2001210654 A JP 2001210654A
Authority
JP
Japan
Prior art keywords
film
withstand voltage
type
substrate
sige
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP2000020153A
Other languages
Japanese (ja)
Inventor
Kouji Nakano
浩児 中野
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Heavy Industries Ltd
Original Assignee
Mitsubishi Heavy Industries Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Heavy Industries Ltd filed Critical Mitsubishi Heavy Industries Ltd
Priority to JP2000020153A priority Critical patent/JP2001210654A/en
Publication of JP2001210654A publication Critical patent/JP2001210654A/en
Withdrawn legal-status Critical Current

Links

Abstract

PROBLEM TO BE SOLVED: To provide the manufacturing method of a semiconductor thin film, which can conduct inactive processing and cleaning processing, on an exposed part in the p-n junction face of the semiconductor thin film in a short time at a room temperature and has the characteristic in withstand voltage of high productivity. SOLUTION: A second conductive SiGe film is laminated on a first conductive Si substrate. The p-n junction face is exposed by etching. A laminated body in a state where the p-n junction face is exposed is irradiated with an ultraviolet ray and the cleaning processing and the inactive processing are conducted.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、バイポーラトラン
ジスタおよび整流器等の半導体装置に用いられるSi
系、SiGe系の耐電圧性を有する半導体薄膜の製造方
法に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device used for a semiconductor device such as a bipolar transistor and a rectifier.
The present invention relates to a method for producing a semiconductor thin film having a withstand voltage based on SiGe or SiGe.

【0002】[0002]

【従来の技術】例えばSi/SiGe/Si三層構造の
バイポーラトランジスタを製造する場合について図3を
参照して説明する。
2. Description of the Related Art A case of manufacturing a bipolar transistor having a three-layer structure of Si / SiGe / Si will be described with reference to FIG.

【0003】まず、コレクタとしての第1導電型Si基
板51(例えばn型Si)上にベース層となる第2導電
型SiGe膜52(例えばp型SiGe)を成膜し、こ
の上にさらにエミッタ層となる第1導電型Si膜53
(例えばn型Si)を成膜する(工程S1)。次いで、
第1導電型Si膜53(エミッタ層)を第2導電型Si
Ge膜52(ベース層)が露出するまで反応性イオンエ
ッチング法やミリング法を用いてドライエッチングし、
電極を形成すべきベース面54を露出させる(工程S
2)。さらに積層体の側面部をウェットエッチング法等
によりエッチングし、メサエッチング部55を形成する
(工程S3)。
First, a second conductivity type SiGe film 52 (eg, p-type SiGe) serving as a base layer is formed on a first conductivity type Si substrate 51 (eg, n-type Si) as a collector, and an emitter is further formed thereon. First conductivity type Si film 53 serving as a layer
A film (for example, n-type Si) is formed (Step S1). Then
The first conductivity type Si film 53 (emitter layer) is
Dry etching using a reactive ion etching method or a milling method until the Ge film 52 (base layer) is exposed,
Exposing a base surface 54 on which an electrode is to be formed (step S
2). Further, the side surface of the stacked body is etched by a wet etching method or the like to form a mesa etched portion 55 (step S3).

【0004】次に、例えば酸素(O2)ガス雰囲気下で
加熱することにより積層体をドライ酸化し、その表面に
厚さ10nm程度の酸化膜56を形成する(工程S
4)。この熱酸化工程S4では、高温で第2導電型Si
Ge膜52の電気特性ができるだけ劣化しないようにす
る必要があるが、750℃前後の温度での試料の加熱
と、2〜10時間程度の酸化時間とを要している。この
酸化膜56は半導体pn接合面でのリーク電流を防止
し、バイポーラトランジスタの耐電圧特性を保持するた
めに必要なものである。
Next, the laminated body is dry-oxidized by, for example, heating in an oxygen (O 2 ) gas atmosphere to form an oxide film 56 having a thickness of about 10 nm on the surface thereof (step S).
4). In this thermal oxidation step S4, the second conductivity type Si
It is necessary to keep the electrical characteristics of the Ge film 52 from deteriorating as much as possible, but it requires heating the sample at a temperature of about 750 ° C. and an oxidation time of about 2 to 10 hours. This oxide film 56 is necessary to prevent a leakage current at the semiconductor pn junction surface and to maintain the withstand voltage characteristics of the bipolar transistor.

【0005】さらに、常法により電極を形成すべき箇所
の酸化膜56を選択的に除去した後、全面に金属アルミ
ニウムを蒸着し、パターニング行なうことにより、コレ
クタ電極57、べース電極58及びエミッタ電極59を
それぞれ形成する(工程S5)。このようにしてSi/
SiGe/Si三層構造のバイポーラトランジスタが得
られる。
Further, after selectively removing the oxide film 56 at a place where an electrode is to be formed by a conventional method, metal aluminum is vapor-deposited on the entire surface and patterned to form a collector electrode 57, a base electrode 58 and an emitter. The electrodes 59 are formed (step S5). Thus, Si /
A bipolar transistor having a SiGe / Si three-layer structure is obtained.

【0006】[0006]

【発明が解決しようとする課題】しかしながら従来の製
造方法においては、試料を高温域に長時間保持する必要
があり、この長時間の熱酸化処理においてドーピングプ
ロファイルが劣化する。また、熱酸化処理に長時間を要
するので、生産性が低い。このような問題点は整流器等
の他の半導体装置においても同様である。
However, in the conventional manufacturing method, it is necessary to hold the sample in a high temperature region for a long time, and the doping profile is deteriorated by the long-time thermal oxidation treatment. Further, since the thermal oxidation process requires a long time, the productivity is low. Such a problem also applies to other semiconductor devices such as a rectifier.

【0007】本発明は上記の課題を解決するためになさ
れたものであって、Si基板とSiGe膜とのpn接合
面、およびSiGe膜とSi膜とのpn接合面の露出す
る部分を室温で短時間に不活性化処理および清浄化処理
することができる高生産性の耐電圧性を有する半導体薄
膜の製造方法を提供することを目的とする。
SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and is intended to solve the problem at room temperature by exposing the pn junction between the Si substrate and the SiGe film and the exposed pn junction between the SiGe film and the Si film. It is an object of the present invention to provide a method of manufacturing a semiconductor thin film having high withstand voltage and high productivity, which can perform inactivation treatment and cleaning treatment in a short time.

【0008】[0008]

【課題を解決するための手段】本発明に係る耐電圧性を
有する半導体薄膜の製造方法は、第1導電型Si基板上
に第2導電型SiGe膜を積層する工程と、エッチング
によりpn接合面を露出させる工程と、このpn接合面
が露出した状態の積層体に対して大気雰囲気中で紫外線
を照射して清浄化処理および不活性化処理を行なう工程
と、を具備することを特徴とする。
According to the present invention, there is provided a method of manufacturing a semiconductor thin film having a withstand voltage according to the present invention, comprising the steps of: laminating a second conductivity type SiGe film on a first conductivity type Si substrate; And performing a cleaning treatment and an inactivation treatment by irradiating the laminated body with the pn junction surface exposed to ultraviolet rays in an air atmosphere. .

【0009】なお、紫外線は室温下で照射されることが
最も好ましいが、室温より少し高めの温度としてもよ
い。ただし、基板温度を上昇させることによる自然酸化
を防ぐために紫外線照射時の温度は100℃を超えない
ことが望ましい。また、紫外線照射時間は数分間である
ことが好ましく、1〜2分間とすることが最も好まし
い。また、紫外線の波長は100〜300nmの範囲と
することが好ましい。
It is most preferable that the ultraviolet ray is irradiated at room temperature, but the temperature may be slightly higher than room temperature. However, in order to prevent spontaneous oxidation caused by increasing the substrate temperature, it is desirable that the temperature at the time of ultraviolet irradiation does not exceed 100 ° C. The ultraviolet irradiation time is preferably several minutes, and most preferably 1-2 minutes. Further, the wavelength of the ultraviolet light is preferably in the range of 100 to 300 nm.

【0010】本発明においては、大気中に特定波長の紫
外線を照射することによりオゾンが生成され、この生成
オゾンがpn接合面での酸化膜の形成および不純物(例
えば油脂などの有機物)の分解除去がなされる。
In the present invention, ozone is generated by irradiating the atmosphere with ultraviolet rays having a specific wavelength, and the generated ozone forms an oxide film on the pn junction surface and decomposes and removes impurities (eg, organic substances such as oils and fats). Is made.

【0011】[0011]

【発明の実施の形態】以下、添付の図面を参照しながら
本発明の種々の好ましい実施の形態について説明する。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Various preferred embodiments of the present invention will be described below with reference to the accompanying drawings.

【0012】(実施例1)図1を参照しながら本発明の
第1の実施例としてSi/SiGe/Si三層構造のn
pn型バイポーラトランジスタを製造する場合について
説明する。
(Embodiment 1) Referring to FIG. 1, as a first embodiment of the present invention, n having a three-layer structure of Si / SiGe / Si
A case where a pn-type bipolar transistor is manufactured will be described.

【0013】まず、コレクタ層となるべきn型Si基板
1(厚さ0.5mm)をCVD炉内に装入し、基板温度
を700〜800℃に上昇させてプロセスガスを供給す
ることにより、Si基板1上に厚さが約400nmのp
型SiGe膜2を気相成長法により成膜した。このp型
SiGe膜2はベース層となるべきものである。次い
で、CVD炉内を排気し、他のプロセスガスを供給する
ことによりp型SiGe膜2上に厚さが約600nmの
n型Si膜3を成膜する(工程S11)。このn型Si
膜3はエミッタ層となるべきものである。なお、成膜手
段にはCVD装置の他にスパッタ装置を用いてもよい。
First, an n-type Si substrate 1 (thickness 0.5 mm) to be a collector layer is charged into a CVD furnace, and the substrate temperature is increased to 700 to 800 ° C. to supply a process gas. On a Si substrate 1, a p of about 400 nm
Type SiGe film 2 was formed by vapor phase epitaxy. This p-type SiGe film 2 is to be a base layer. Next, the inside of the CVD furnace is evacuated, and another process gas is supplied to form an n-type Si film 3 having a thickness of about 600 nm on the p-type SiGe film 2 (step S11). This n-type Si
The film 3 is to be an emitter layer. In addition, a sputtering apparatus may be used as the film forming means in addition to the CVD apparatus.

【0014】次に、ベース層となるべきp型SiGe膜
2が完全に露出するまでn型Si膜3およびp型SiG
e膜2を反応性イオンエッチング法により選択エッチン
グし、電極を形成すべきベース面4を露出させる(工程
S12)。さらに積層体の側面部をウェットエッチング
法によりエッチングし、メサエッチング部5を形成する
(工程S13)。
Next, until the p-type SiGe film 2 to be a base layer is completely exposed, the n-type Si film 3 and the p-type SiG
The e film 2 is selectively etched by a reactive ion etching method to expose the base surface 4 on which an electrode is to be formed (step S12). Further, the side surfaces of the stacked body are etched by the wet etching method to form the mesa-etched portions 5 (Step S13).

【0015】処理室内を大気雰囲気とし、光源6を点灯
して100〜300nmの波長範囲をもつ紫外線を大気
に照射する。紫外線の照射時間は約1分間とした。紫外
線光源6には水銀ランプを用いた。紫外線照射により大
気中の酸素からオゾン7が生成される(工程S14)。
この生成オゾン7は室温(25℃前後)下で試料表面の
有機系の不純物(油脂など)を分解除去するので、試料
表面が清浄化される。同時に露出する半導体表面が酸化
され、厚さ2nm程度の薄い酸化膜8が形成される(工
程S15)。
The atmosphere inside the processing chamber is set to the atmosphere, and the light source 6 is turned on to irradiate the atmosphere with ultraviolet rays having a wavelength range of 100 to 300 nm. The irradiation time of the ultraviolet rays was about 1 minute. A mercury lamp was used as the ultraviolet light source 6. Ozone 7 is generated from oxygen in the atmosphere by ultraviolet irradiation (step S14).
The generated ozone 7 decomposes and removes organic impurities (such as oils and fats) on the sample surface at room temperature (around 25 ° C.), so that the sample surface is cleaned. At the same time, the exposed semiconductor surface is oxidized to form a thin oxide film 8 having a thickness of about 2 nm (step S15).

【0016】さらに、常法により電極を形成すべき箇所
に対する前記酸化膜8を選択的に除去した後に、全面に
アルミニウムを蒸着し、パターニングによりコレクタ電
極9、ベース電極10及びエミッタ電極11を形成した
(工程S16)。これにより図示のnpn型バイポーラ
トランジスタを得た。
Further, after selectively removing the oxide film 8 from a portion where an electrode is to be formed, aluminum is deposited on the entire surface, and a collector electrode 9, a base electrode 10 and an emitter electrode 11 are formed by patterning. (Step S16). Thus, the illustrated npn-type bipolar transistor was obtained.

【0017】このようにして製造されたバイポーラトラ
ンジスタのコレクタ/べース間の耐電圧は、従来の酸化
膜がある場合と同程度の耐圧を保持していることが確認
できた。これは、室温で短時間に半導体pn界面の不活
性化と清浄化処理が実現していることを示している。
It has been confirmed that the withstand voltage between the collector and the base of the bipolar transistor manufactured as described above has a breakdown voltage substantially equal to that of a conventional oxide film. This indicates that inactivation and cleaning of the interface of the semiconductor pn are realized in a short time at room temperature.

【0018】本実施例によれば、従来方法では数時間を
要していたバイポーラトランジスタの耐電圧性向上のた
めの処理を僅か数分間で完了させることができ、生産性
を飛躍的に向上させることができた。
According to this embodiment, the process for improving the withstand voltage of the bipolar transistor, which took several hours in the conventional method, can be completed in only a few minutes, and the productivity is dramatically improved. I was able to.

【0019】なお、上記実施例では,npn型バイポー
ラトランジスタの場合について述べたが、本発明はこれ
に限られず、pnp型バイポーラトランジスタの場合に
も同様に適用することができる。
In the above embodiment, the case of an npn-type bipolar transistor has been described. However, the present invention is not limited to this and can be similarly applied to a case of a pnp-type bipolar transistor.

【0020】また、上記実施例では、室温下で紫外線照
射時間を約1分間としたが、温度条件を室温より若干高
めに設定してもよいし、さらに紫外線照射時間を1分間
以上5分間以下の範囲内で長くしてもよい。
Further, in the above embodiment, the ultraviolet irradiation time at room temperature is about 1 minute, but the temperature condition may be set slightly higher than room temperature, and the ultraviolet irradiation time may be 1 minute or more and 5 minutes or less. May be lengthened within the range.

【0021】(実施例2)次に、図2を参照しながら本
発明の第2の実施例としてSi/SiGe二層構造の整
流器を製造する場合について説明する。
(Embodiment 2) Next, a case of manufacturing a rectifier having a two-layered structure of Si / SiGe will be described as a second embodiment of the present invention with reference to FIG.

【0022】まず、カソードとなるべきn型Si基板2
1(厚さ0.5mm)をCVD炉内に装入し、基板温度
を700〜800℃に上昇させてプロセスガスを供給す
ることにより、Si基板21上に厚さが約400nmの
p型SiGe膜2を成膜する(工程S21)。
First, an n-type Si substrate 2 to be a cathode
1 (0.5 mm thick) is loaded into a CVD furnace, and the substrate temperature is increased to 700 to 800 ° C. to supply a process gas, whereby p-type SiGe having a thickness of about 400 nm is formed on the Si substrate 21. The film 2 is formed (Step S21).

【0023】続いて、p型SiGe膜22の上方からイ
オン注入器23によりボロンイオン23を注入する。そ
の後、窒素雰囲気中で1000℃の温度に1〜3分間保
持するアニール処理を行ない、注入イオンの活性化を行
ない、p型SiGe膜22表面にボロンの高濃度層24
を形成する(工程S22)。整流器側面は、ウェットエ
ッチング等の手法によりエッチングし、メサエッチング
部25とする(工程S23)。
Subsequently, boron ions 23 are implanted from above the p-type SiGe film 22 by an ion implanter 23. Thereafter, an annealing process is performed at a temperature of 1000 ° C. for 1 to 3 minutes in a nitrogen atmosphere to activate the implanted ions, and a boron high concentration layer 24 is formed on the surface of the p-type SiGe film 22.
Is formed (Step S22). The side surface of the rectifier is etched by a method such as wet etching to form a mesa etching portion 25 (step S23).

【0024】処理室内を大気雰囲気とし、光源26を点
灯して100〜300nmの波長範囲をもつ紫外線を大
気に照射する。紫外線の照射時間は約1分間とした。紫
外線照射により大気中の酸素からオゾン27が生成され
る(工程S24)。この生成オゾン27は室温(25℃
前後)下で試料表面の有機系の不純物(油脂など)を分
解除去するので、試料表面が清浄化される。同時に露出
する半導体表面が酸化され、厚さ2nm程度の薄い酸化
膜28が形成される(工程S25)。
The atmosphere inside the processing chamber is turned on, and the light source 26 is turned on to irradiate the atmosphere with ultraviolet rays having a wavelength range of 100 to 300 nm. The irradiation time of the ultraviolet rays was about 1 minute. Ozone 27 is generated from oxygen in the atmosphere by ultraviolet irradiation (step S24). This generated ozone 27 is at room temperature (25 ° C.
Under (before and after), organic impurities (such as fats and oils) on the sample surface are decomposed and removed, so that the sample surface is cleaned. At the same time, the exposed semiconductor surface is oxidized to form a thin oxide film 28 having a thickness of about 2 nm (step S25).

【0025】さらに、常法により電極を形成すべき箇所
に対する前記酸化膜28を選択的に除去した後に、全面
にアルミニウムを蒸着し、パターニングによりアノード
電極29とカソード電極30とをそれぞれ形成した(工
程S26)。これにより図示のpn型整流器を得た。
Further, after selectively removing the oxide film 28 at a place where an electrode is to be formed, aluminum is deposited on the entire surface and an anode electrode 29 and a cathode electrode 30 are formed by patterning, respectively (step). S26). Thus, the illustrated pn-type rectifier was obtained.

【0026】このようにして製造された整流器のアノー
ド/カソード間の耐電圧は、従来の酸化膜がある場合と
同程度の耐圧を保持できる。これは、室温で短時間に半
導体pn界面の不活性化及び清浄化処理が実現している
ことを示している。
The withstand voltage between the anode and the cathode of the rectifier thus manufactured can maintain the same withstand voltage as in the case where the conventional oxide film is provided. This indicates that the passivation and cleaning treatment of the semiconductor pn interface is realized in a short time at room temperature.

【0027】本実施例によれば、従来方法では数時間を
要していた整流器の耐電圧性向上のための処理を僅か数
分間で完了させることができ、生産性を飛躍的に向上さ
せることができた。
According to this embodiment, the process for improving the withstand voltage of the rectifier, which required several hours in the conventional method, can be completed in only a few minutes, and the productivity is dramatically improved. Was completed.

【0028】なお、上記実施例では、Si/SiGe−
pn型整流器の場合について述べたが、本発明はこれに
限られずSi/Si−pn型整流器、Si/SiGe−
np型整流器、Si/Si−np型整流器等についても
同様に適用することができる。
In the above embodiment, Si / SiGe-
Although the case of a pn-type rectifier has been described, the present invention is not limited to this, and a Si / Si-pn-type rectifier, a Si / SiGe-
The same can be applied to an np rectifier, a Si / Si-np rectifier, and the like.

【0029】[0029]

【発明の効果】本発明によれば、Si基板とSiGe膜
とのpn接合面、およびSiGe膜とSi膜のpn接合
面のうち露出する部分を、室温で、短時間に不活性化処
理および清浄化処理することができるので、所望の耐電
圧特性を有する半導体薄膜の生産性が大幅に向上する。
According to the present invention, the exposed portions of the pn junction between the Si substrate and the SiGe film and the pn junction between the SiGe film and the Si film are subjected to the passivation treatment at room temperature in a short time. Since the cleaning treatment can be performed, the productivity of a semiconductor thin film having a desired withstand voltage characteristic is greatly improved.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の第1の実施形態に係る耐電圧性を有す
る半導体薄膜(Si/SiGe/Siバイポーラトラン
ジスタ)の製造方法を示すプロセスフローチャート及び
断面模式図。
FIG. 1 is a process flowchart and a schematic cross-sectional view showing a method for manufacturing a semiconductor thin film (Si / SiGe / Si bipolar transistor) having a withstand voltage according to a first embodiment of the present invention.

【図2】本発明の第2の実施形態に係る耐電圧性を有す
る半導体薄膜(Si/SiGe整流器)の製造方法を示
すプロセスフローチャート及び断面模式図。
FIGS. 2A and 2B are a process flowchart and a schematic cross-sectional view illustrating a method for manufacturing a semiconductor thin film (Si / SiGe rectifier) having a withstand voltage according to a second embodiment of the present invention.

【図3】従来の製造方法を示すプロセスフローチャート
及び断面模式図。
FIG. 3 is a process flowchart and a schematic cross-sectional view showing a conventional manufacturing method.

【符号の説明】[Explanation of symbols]

1;n型Si基板、 2;p型SiGe膜、 3;n型Si膜、 4;べース面、 5;メサエッチング部、 6;紫外線光源、 7;オゾン、 8;酸化膜、 9;コレクタ電極、 10;ベース電極、 11;エミッタ電極。 21;n型Si基板、 22;p型SiGe膜、 23;ボロンイオン、 24;高濃度p型SiGe層、 25;メサエッチング部、 26;紫外線光源、 27;オゾン、 28;酸化膜、 29;アノード電極、 30;カソード電極。 1; n-type Si substrate; 2; p-type SiGe film; 3; n-type Si film; 4; base surface; 5; mesa etching portion; 6; ultraviolet light source; Collector electrode, 10; base electrode, 11; emitter electrode. 21; n-type Si substrate; 22; p-type SiGe film; 23; boron ion; 24; high-concentration p-type SiGe layer; 25; mesa-etched portion; Anode electrode, 30; cathode electrode.

Claims (5)

【特許請求の範囲】[Claims] 【請求項1】 第1導電型Si基板上に第2導電型Si
Ge膜を積層する工程と、エッチングによりpn接合面
を露出させる工程と、このpn接合面が露出した状態の
積層体に対して大気雰囲気中で紫外線を照射して清浄化
処理および不活性化処理を行なう工程と、を具備するこ
とを特徴とする耐電圧性を有する半導体薄膜の製造方
法。
A first conductive type Si substrate on a first conductive type Si substrate;
A step of laminating a Ge film, a step of exposing a pn junction surface by etching, and a cleaning treatment and an inactivation treatment by irradiating the laminated body with the pn junction surface exposed to ultraviolet rays in an air atmosphere. A method of manufacturing a semiconductor thin film having a withstand voltage.
【請求項2】 基板を実質的に加熱することなくpn接
合面を不活性化処理または清浄化処理することを特徴と
する請求項1記載の方法。
2. The method according to claim 1, wherein the pn junction surface is passivated or cleaned without substantially heating the substrate.
【請求項3】 pn接合面の不活性化処理と清浄化処理
とを同時に行なうことを特徴とする請求項1記載の方
法。
3. The method according to claim 1, wherein the passivation treatment and the cleaning treatment of the pn junction surface are performed simultaneously.
【請求項4】 紫外線は室温下で照射されることを特徴
とする請求項1記載の方法。
4. The method according to claim 1, wherein the ultraviolet light is irradiated at room temperature.
【請求項5】 紫外線照射時間は数分間であることを特
徴とする請求項1記載の方法。
5. The method according to claim 1, wherein the ultraviolet irradiation time is several minutes.
JP2000020153A 2000-01-28 2000-01-28 Method of manufacturing semiconductor film having characteristic in withstand voltage Withdrawn JP2001210654A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2000020153A JP2001210654A (en) 2000-01-28 2000-01-28 Method of manufacturing semiconductor film having characteristic in withstand voltage

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2000020153A JP2001210654A (en) 2000-01-28 2000-01-28 Method of manufacturing semiconductor film having characteristic in withstand voltage

Publications (1)

Publication Number Publication Date
JP2001210654A true JP2001210654A (en) 2001-08-03

Family

ID=18546763

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2000020153A Withdrawn JP2001210654A (en) 2000-01-28 2000-01-28 Method of manufacturing semiconductor film having characteristic in withstand voltage

Country Status (1)

Country Link
JP (1) JP2001210654A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6518197B2 (en) * 2001-04-03 2003-02-11 Mitsubishi Heavy Industries, Ltd. Method for manufacturing semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6518197B2 (en) * 2001-04-03 2003-02-11 Mitsubishi Heavy Industries, Ltd. Method for manufacturing semiconductor device

Similar Documents

Publication Publication Date Title
JP2001210654A (en) Method of manufacturing semiconductor film having characteristic in withstand voltage
JP3647850B2 (en) Semiconductor device and manufacturing method thereof
JP5672659B2 (en) Method for manufacturing silicon carbide semiconductor device
TW594917B (en) Method for forming gate sidewall spacer
JP2771066B2 (en) Method for manufacturing semiconductor device
JPH06224416A (en) Mos field effect transistor and its manufacture, and semiconductor device using mos field effect transistor
JPS5933255B2 (en) Manufacturing method of semiconductor device
JPH05267665A (en) Thin-film transistor
JPH04367276A (en) Thin film transistor and manufacture thereof
JP2008021723A (en) Manufacturing method of semiconductor device
JP4061413B2 (en) Manufacturing method of semiconductor device
JP3084089B2 (en) Semiconductor device substrate and method of manufacturing the same
JP2988067B2 (en) Manufacturing method of insulated field effect transistor
JPH03173131A (en) Manufacture of semiconductor device
JPH027420A (en) Manufacture of semiconductor device
JPS58110033A (en) Semiconductor device and manufacture thereof
JP2000022157A (en) Fabrication of thin film transistor
JPS63110748A (en) Manufacture of semiconductor device
JP2007109785A (en) Semiconductor device and its manufacturing method
JP2002252343A (en) Semiconductor device and manufacturing method of the same
JPH0191417A (en) Semiconductor device and manufacture thereof
JPS61187233A (en) Formation of electrodes in semiconductor device
JPH0974206A (en) Semiconductor device and manufacture thereof
JPH10270706A (en) Manufacture of semiconductor device
JPH04354328A (en) Production of semiconductor device

Legal Events

Date Code Title Description
A300 Withdrawal of application because of no request for examination

Free format text: JAPANESE INTERMEDIATE CODE: A300

Effective date: 20070403