JPH0481338B2 - - Google Patents

Description

[Detailed description of the invention]

[Technical Field of the Invention] The present invention relates to a method for manufacturing a MOS integrated circuit using a semiconductor single crystal film on an insulating single crystal substrate. [Technical background of the invention and its problems] Using a semiconductor single crystal film on an insulating single crystal substrate
MOS integrated circuits are advantageous over those using semiconductor substrates in terms of their structure, high speed, and high density. However, the semiconductor single crystal film contains a larger amount of lattice defects than a semiconductor substrate made of the same element. Therefore, the electrical characteristics of the device are also poor. Below, we will discuss in detail the problems of a MOS integrated circuit using a single crystal silicon film (SOS) film on a sapphire substrate as a representative example. Compared to MOS devices made using silicon substrates, MOS devices using SOS films have drawbacks such as lower carrier mobility and increased drain leakage current. Incidentally, in an inverter circuit that is a basic circuit constituting an integrated circuit, an N-channel E-type (enhancement type) MOS is used as an active element in the case of an N-channel E/DMOS and a complementary MOS. In the N-channel E-type MOS, the channel is formed only near the surface of the silicon film. Therefore,
In order to improve carrier mobility in the channel region, it is necessary to reduce lattice defects near the surface of the silicon film. Another problem with N-channel E-type MOS is that the drain leakage current is large.
This leakage current occurs because electrons are induced on the silicon side near the silicon-sapphire interface and conduction occurs between the source and drain (interface leakage current). Therefore, when the lattice defect density of the silicon film near the interface decreases, the electrical conductivity in that region increases, so that leakage current also increases. Therefore, if the lattice defect density of the entire silicon film is reduced, the carrier mobility increases, but
This is not preferable because leakage current also increases. Therefore, it is required to reduce the lattice defect density only in the vicinity of the silicon film surface. On the other hand, as a load element, N channel E/
In the case of DMOS, an N-channel D-type (depression type) MOS is used, and in the case of complementary MOS, a P-channel MOS is used. N channel D type MOS
Therefore, it is necessary to reduce the lattice defect density of the entire silicon film for two reasons: a channel region is formed throughout the silicon film and the interfacial leakage current becomes negligibly small. In addition, in P-type channel MOS, unlike N-channel MOS, there is no interface leakage current, and the main component of leakage current is current generated due to lattice defects.
To improve this, it is necessary to reduce the lattice defect density of the entire silicon film. In this way, in order to improve the characteristics of integrated circuits using N-channel D-type MOS and P-channel MOS as load elements, it is necessary to reduce the lattice defect density of the entire silicon film in the region where these load elements are to be formed. is requested. Therefore, the inventors of the present invention previously proposed in Japanese Patent Application No. 56-19008 that they implanted ions into the region where active elements and load elements were to be formed, made the surface side of this region amorphous, and then recrystallized it by heat treatment. The authors disclosed a method in which ions are implanted only in a region where a load element is to be formed, the interface side of this region is made amorphous, and then recrystallized by heat treatment. According to the above method, an N-channel E/D type MOS or complementary type MOS is formed using a 0.3 μm thick single crystal silicon film formed on a sapphire substrate.
Regarding MOS, we were able to improve carrier mobility and reduce leakage current. However, as elements become smaller with advances in LSI technology, there has been a demand for further improvements in carrier mobility and reduction in leakage current. [Object of the Invention] The present invention has been made in view of the above circumstances, and provides a method that can further improve carrier mobility and further reduce leakage current of a semiconductor device formed on an insulating single crystal substrate. This is what I am trying to do. [Summary of the Invention] The method for manufacturing a semiconductor device of the present invention includes forming a thermal oxide film on the surface of a single crystal semiconductor film deposited on an insulating single crystal substrate, removing the thermal oxide film, and then applying a load. Ion implantation is performed only in the region where the element is to be formed, the interface side of this region is made amorphous, and then this amorphous layer is recrystallized by heat treatment, and the region where the active element and the load element are to be formed is further removed. The method is characterized in that the surface side of this region is made amorphous by ion implantation, and then the amorphous layer is recrystallized by heat treatment. According to this method, the crystallinity on the surface side can be improved by forming and removing a thermal oxide film on the semiconductor film surface, and the interface side of the region where the load element is to be formed is made amorphous, resulting in improved crystallinity. The crystallinity on the interface side can be improved by recrystallization using the surface side as a seed crystal, and further, by making the surface side of the region where active elements and load elements are to be formed amorphous, and recrystallizing using the interface side as a seed crystal. Accordingly, the crystallinity on the surface side can be further improved. Therefore, in the region where the active element is formed, the crystallinity is improved only on the surface side, and in the region where the load element is formed, the crystallinity is improved all over from the surface to the interface, so that the active element and load formed in each region are improved. The device has improved carrier mobility and reduced leakage current. [Embodiments of the Invention] Examples of the present invention will be described below with reference to FIGS.
This will be explained with reference to FIGS. () First, a (001) single crystal silicon vapor phase growth film 2 having a thickness of 0.3 μm was epitaxially grown on a sapphire single crystal substrate 1 having a (1012) plane (as shown in FIG. 1a). Next, in a 100% oxygen atmosphere,
Thermal oxidation was performed at 1000° C. for 50 minutes to form a thermal oxide film 3 with a thickness of 500 Å on the surface of the vapor-phase grown film 2 (as shown in FIG. 1B). Subsequently, the thermal oxide film 3 was removed by immersing it in an ammonium fluoride solution for 30 minutes. As a result, the crystallinity of the surface of the vapor-phase grown film 2 was improved (as shown in c in the figure). () Next, a photoresist pattern 5 is formed on the active element region 4 where an N-channel E-type transistor is formed, and this photoresist pattern 5 is
Load element region 6 in which an N-channel D-type or P-channel transistor is formed using as a mask.
Energy that accelerates silicon ions only to
Ion implantation was performed under the conditions of 200 keV and a dose of 1×10 ¹⁵ cm ⁻² . As a result, an amorphous layer 7 was formed on the silicon-sapphire interface side of the load element region 6 (as shown in figure d). Subsequently, after removing the photoresist pattern 5, in an _N2 gas atmosphere,
A heat treatment was performed at 1000° C. for 20 minutes, and the amorphous layer 7 was solid-phase epitaxially grown from the surface side to form a recrystallized layer 8 (as shown in the figure e). () Then the silicon ions are accelerated with energy
Ion implantation was performed under the conditions of 120 keV and a dose of 2×10 ¹⁵ cm ⁻² . As a result, an amorphous layer 9 was formed to a depth of about 0.2 μm from the surface side of the vapor-phase grown film 2 (as shown in the figure f). Subsequently, heat treatment was performed at 1000° C. for 20 minutes in an N ₂ gas atmosphere to remove the amorphous layer 9.
A recrystallized layer 10 was formed by solid-phase epitaxial growth from the silicon-sapphire interface side (as shown in g in the same figure). Through the above steps, the crystallinity of the active element region 4 where an N-channel E-type transistor is formed is improved only on the surface side, and the load element region 6 where an N-channel D-type transistor or a P-channel transistor is formed extends from the surface to the interface. Crystallinity is improved across the board. At this time, an oxide film 3 is formed on the surface of the single-crystal silicon vapor-phase grown film 2 formed in the step shown in FIG. 1a, and then a thermal oxide film 3 is formed in the step shown in FIG. By removing , the crystallinity of the surface region of the vapor grown film 2 is improved. Next, in the process shown in figure d, silicon is ion-implanted only into the load element region 6 to form an amorphous layer 7 on the interface side of this area, and then the surface area is subjected to heat treatment in the process shown in figure e. When the recrystallized layer 8 is formed by solid-phase epitaxial growth using the vapor-phase grown film 2 with improved crystallinity as a seed crystal, the crystallinity on the interface side of this region is improved. Furthermore, the figure f
In the illustrated process, the active element area 4 and the load element area 6 are
After forming an amorphous layer 9 on the surface side by ion-implanting silicon, in the process shown in FIG. If the recrystallized layer 10 is formed by solid-phase epitaxial growth using the recrystallized layer 8 as a seed crystal, the crystallinity on the surface side will be improved. After that, the N-channel E-type transistor shown in FIG. 2 is placed in the active element region 4, and the N-channel D-type transistor shown in FIG. 3 or the P-channel transistor shown in FIG. 4 is placed in the load element region 6 as follows. Manufactured according to normal manufacturing process. () First, a single crystal silicon film on the sapphire substrate 1 was etched to form a silicon island.
At this time, the crystallinity of the silicon island where the N-channel E-type transistor is formed is improved only on the surface side, and the silicon island where the N-channel D-type transistor or P-channel transistor is formed is completely covered from the surface to the interface. The crystallinity has been improved. () Next, thermal oxidation was performed at 950℃ in dry oxygen,
A thermal oxide film with a thickness of 500 Å that will become the gate oxide film was formed on the surface of the silicon island. () Next, a P-type impurity was ion-implanted into the channel region of the silicon island where an N-channel E-type transistor was to be formed, to form a P-type channel region 11. Furthermore, N-type impurity ions were implanted into channel regions of the silicon island where N-channel D-type transistors or P-channel transistors are to be formed to form N-type channel regions 12 and 13. () Next, after depositing N-type polycrystalline silicon on the entire surface, patterning is performed to form the gate electrode 14,
. . . were formed, and the thermal oxide film was etched using the gate electrodes 14, . . . as a mask to form gate oxide films 15, . () Next, N-type impurity or P-type impurity is ion-implanted using the gate electrode 14 as a mask to form an N-channel E-type transistor.
N ⁺ type source and drain regions 16 and 17, N ⁺ type source and drain regions 18 and 19 of an N channel D type transistor or P ⁺ type source and drain regions 20 and 2 of a P channel transistor
1 was formed. () Subsequently, a CVD oxide film 22 was deposited as an interlayer insulating film over the entire surface. () Subsequently, contact holes 23, .
... was formed. Through the above steps, an N-channel E-type transistor as an active element, and an N-channel D-type transistor or a P-channel transistor as a load element were formed. However, according to the method of the present invention, in the N-channel E-type transistor that is an active element, the crystallinity near the interface of the P-type channel region 11 is not improved, and while the interface leakage current can be suppressed, the surface Since the crystallinity in the vicinity is improved, the generated current can be reduced. Therefore, carrier mobility can be improved and drain leakage current can be reduced. In addition, in the N-channel D-type transistor or P-channel transistor that is a load element, the crystallinity is improved in the entire N-type channel region or from the surface of the N-type channel region 13 to the interface, so that the lattice is improved. By reducing the defect density, carrier mobility can be improved and drain leakage current can be reduced. In fact, when carrier mobility and drain leakage current were measured for the N-channel E-type transistor, N-channel D-type transistor, and P-channel transistor manufactured as described above, the results shown in the table below were obtained. Note that the drain leak current is a measured value when the carrier mobility is within the range. In addition, the comparative example is
56-19008, and the reference example is the result for a transistor manufactured using a vapor-phase grown film whose crystallinity has not been improved.

〔Effect of the invention〕

As detailed above, according to the method for manufacturing a semiconductor device of the present invention, it is possible to further improve the carrier mobility of both active elements and load elements, further reduce drain leakage current, and increase the speed of semiconductor devices. This has the remarkable effect of significantly improving reliability.

[Brief explanation of drawings]

Figures 1a to 1g are cross-sectional views showing step-by-step a method for improving the crystallinity of a single-crystal silicon film on a sapphire substrate in an embodiment of the present invention, and Figure 2 is a cross-sectional view showing a method for improving the crystallinity of a single crystal silicon film on a sapphire substrate in an embodiment of the present invention. FIG. 3 is a cross-sectional view of an N-channel D-type transistor obtained by the same method, and FIG. 4 is a cross-sectional view of a P-channel transistor obtained by the same method. DESCRIPTION OF SYMBOLS 1...Sapphire substrate, 2...Single crystal silicon vapor phase growth film, 3...Thermal oxide film, 4...Active element region, 5...Photoresist pattern, 6...Load element region, 7, 9...Non Crystalline layer, 8, 10... Recrystallization layer, 11... P-type channel region, 12, 13...
...N-type channel region, 14...gate electrode, 15
...Gate oxide film, 16, 17, 18, 19...
N ⁺ type source, drain region, 20, 21...P ⁺
type source, drain region, 22...CVD oxide film,
23...Contact hole, 24...Al wiring.

Claims (1)

[Claims] 1 N-channel E/D type MOS or complementary type MOS on a single crystal semiconductor film deposited on an insulating single crystal substrate
In manufacturing a semiconductor device including a MOS transistor, a step of forming a thermal oxide film on the surface of the single crystal semiconductor film and then removing the thermal oxide film, and performing ion implantation only in a region where a load element is to be formed, A step of making the interface side of this region with the insulating single crystal substrate amorphous, a step of recrystallizing the amorphous layer by heat treatment, and ion implantation into the region where active elements and load elements are to be formed. A method of manufacturing a semiconductor device, comprising the steps of: amorphizing the surface side of the region by performing a heat treatment; and recrystallizing the amorphous layer by heat treatment.