JPS5665245A - Decode control circuit - Google Patents

Decode control circuit

Info

Publication number
JPS5665245A
JPS5665245A JP14086979A JP14086979A JPS5665245A JP S5665245 A JPS5665245 A JP S5665245A JP 14086979 A JP14086979 A JP 14086979A JP 14086979 A JP14086979 A JP 14086979A JP S5665245 A JPS5665245 A JP S5665245A
Authority
JP
Japan
Prior art keywords
counter
decode
control circuit
signal
output
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP14086979A
Other languages
Japanese (ja)
Inventor
Tadayoshi Yoshimura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP14086979A priority Critical patent/JPS5665245A/en
Publication of JPS5665245A publication Critical patent/JPS5665245A/en
Pending legal-status Critical Current

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Landscapes

  • Compression, Expansion, Code Conversion, And Decoders (AREA)

Abstract

PURPOSE: To make it possible to simplify the decode circuit of an output of the counter, by controlling the initial state of the counter of (n) bits.
CONSTITUTION: The decode control circuit is constituted of a 4 bit counter C1 and a decoder D1 in order to generate the timing. In this case, when a fundamental clock signal is input to the counter C1, the state of the counter C1 is decoded and various timing signals are generated by its decode signal, the initial state of the counter C1 is set and controlled in accordance with the decode signal so that the necessary decode signal can be output by the minimum number of decoders. In this way, in case when outputs to be taken out as decode signals are a few, the number of IC for decoding can be decreased.
COPYRIGHT: (C)1981,JPO&Japio
JP14086979A 1979-10-31 1979-10-31 Decode control circuit Pending JPS5665245A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14086979A JPS5665245A (en) 1979-10-31 1979-10-31 Decode control circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14086979A JPS5665245A (en) 1979-10-31 1979-10-31 Decode control circuit

Publications (1)

Publication Number Publication Date
JPS5665245A true JPS5665245A (en) 1981-06-02

Family

ID=15278632

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14086979A Pending JPS5665245A (en) 1979-10-31 1979-10-31 Decode control circuit

Country Status (1)

Country Link
JP (1) JPS5665245A (en)

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